package hardcaml

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Definition of clock, reset and clear signals for sequential logic (ie registers).

include module type of struct include Signal.Reg_spec_ end

Reg_spec_ is a register specification. It is named Reg_spec_ rather than Reg_spec so that people consistently use the name Hardcaml.Reg_spec rather than Hardcaml.Signal.Reg_spec_.

val sexp_of_t : t -> Sexplib0.Sexp.t
val create : ?clear:Signal.signal -> ?reset:Signal.signal -> Base.unit -> clock:Signal.signal -> t
val override : ?clock:Signal.signal -> ?clock_edge:Edge.t -> ?reset:Signal.signal -> ?reset_edge:Edge.t -> ?reset_to:Signal.signal -> ?clear:Signal.signal -> ?clear_level:Level.t -> ?clear_to:Signal.signal -> ?global_enable:Signal.signal -> t -> t
val clock : t -> Signal.signal
val clear : t -> Signal.signal
val reset : t -> Signal.signal