package hardcaml

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package hardcaml
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type 'a t
val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
val iter : 'a t -> f:('a -> Base.unit) -> Base.unit
val iter2 : 'a t -> 'b t -> f:('a -> 'b -> Base.unit) -> Base.unit
val map : 'a t -> f:('a -> 'b) -> 'b t
val map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
val to_list : 'a t -> 'a Base.list
val t : (Base.string * Base.int) t
include Base.Equal.S1 with type 'a t := 'a t
val equal : 'a Base__Equal.equal -> 'a t Base__Equal.equal
val port_names : Base.string t

RTL names specified in the interface definition - commonly also the OCaml field name.

val port_widths : Base.int t

Bit widths specified in the interface definition.

val to_alist : 'a t -> (Base.string * 'a) Base.list

Create association list indexed by field names.

val of_alist : (Base.string * 'a) Base.list -> 'a t

Create interface from association list indexed by field names

val zip : 'a t -> 'b t -> ('a * 'b) t
val zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t
val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t
val zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t
val map3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> 'd) -> 'd t
val map4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> 'e) -> 'e t
val map5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> 'f) -> 'f t
val iter3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> Base.unit) -> Base.unit
val iter4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> Base.unit) -> Base.unit
val iter5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> Base.unit) -> Base.unit
val fold : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc) -> 'acc
val fold2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc) -> 'acc
val scan : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc * 'b) -> 'b t
val scan2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc * 'c) -> 'c t
val offsets : ?rev:Base.bool -> Base.unit -> Base.int t

Offset of each field within the interface. The first field is placed at the least significant bit, unless the rev argument is true.

val of_interface_list : 'a t Base.list -> 'a Base.list t

Take a list of interfaces and produce a single interface where each field is a list.

val to_interface_list : 'a Base.list t -> 'a t Base.list

Create a list of interfaces from a single interface where each field is a list. Raises if all lists don't have the same length.

module All (M : Base.Monad.S) : sig ... end

Similar to Monad.all for lists -- combine and lift the monads to outside the interface.

val or_error_all : 'a Base.Or_error.t t -> 'a t Base.Or_error.t

Equivalent to All(Or_error).all. This is made a special case for convenience.

module type Comb = sig ... end
module Make_comb (Comb : Comb.S) : Comb with type comb = Comb.t
module Names_and_widths : sig ... end
val ast : Ast.t
val of_enum : (module Comb.S with type t = 'a) -> Enum.t -> 'a t
val to_enum : Bits.t t -> Enum.t Base.Or_error.t
val to_enum_exn : Bits.t t -> Enum.t
val (==:) : (module Comb.S with type t = 'a) -> 'a t -> 'a t -> 'a
val match_ : (module Comb.S with type t = 'a) -> ?default:'a -> 'a t -> (Enum.t * 'a) Base.list -> 'a
val to_raw : 'a t -> 'a
type 'a outer := 'a t
module Of_signal : sig ... end
module Of_bits : sig ... end
module Of_always : sig ... end
val sim_set : Bits.t Base.ref t -> Enum.t -> Base.unit

Set an input port in simulation to a concrete Enum value.

val sim_set_raw : Bits.t Base.ref t -> Bits.t -> Base.unit

Similar to sim_set, but operates on raw Bits.t instead.

val sim_get : Bits.t Base.ref t -> Enum.t Base.Or_error.t

Read an output port from simulation to a concreate Enum value. Returns Ok enum when the Bits.t value can be parsed, and Error _ when the value is unhandled.

val sim_get_exn : Bits.t Base.ref t -> Enum.t

Equivalent to ok_exn (sim_get x)

val sim_get_raw : Bits.t Base.ref t -> Bits.t

Similar to sim_get, but operates on raw Bits.t instead. This doesn't return _ Or_error.t. Undefined values will be returned as it is.

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