Cycle accurate simulator
module Port_list : sig ... endmodule Digest : sig ... endmodule Config : sig ... endtype t_port_list = (Port_list.t, Port_list.t) tval cycle : (_, _) t -> Base.unitadvance by 1 clock cycle (check->comb->seq->comb)
val cycle_check : (_, _) t -> Base.unitcheck inputs are valid before a simulation cycle
val cycle_before_clock_edge : (_, _) t -> Base.unitupdate combinatorial logic before clock edge and relative to new inputs.
val cycle_at_clock_edge : (_, _) t -> Base.unitupdate sequential logic - registers and memories.
val cycle_after_clock_edge : (_, _) t -> Base.unitupdate combinatorial logic after clock edge
val reset : (_, _) t -> Base.unitreset simulator
Get output port given a name. If clock_edge is Before the outputs are computed prior to the clock edge - After means the outputs are computed after the clock edge.
val inputs : ('i, _) t -> 'ival in_ports : (_, _) t -> Port_list.tval out_ports : ?clock_edge:Side.t -> (_, _) t -> Port_list.tval internal_ports : (_, _) t -> Port_list.tget list of internal nodes
val lookup_signal : (_, _) t -> Signal.Uid.t -> Bits.t Base.refval lookup_reg : (_, _) t -> Signal.Uid.t -> Bits.t Base.refmodule Violated_or_not : sig ... endval results_of_assertions :
(_, _) t ->
Violated_or_not.t Base.Map.M(Base.String).tval create : ?config:Config.t -> Circuit.t -> t_port_listconstruct a simulator from a circuit
module Combine_error : sig ... endval combine :
?port_sets_may_differ:Base.bool ->
?on_error:(Combine_error.t -> Base.unit) ->
('i, 'o) t ->
('i, 'o) t ->
('i, 'o) tCombine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and on_error is called if a difference is found. By default, on_error raises.
The simulators should have the same input and output port sets, unless port_sets_may_differ is true, in which case only ports which exist on both simulators are checked.
module With_interface (I : Interface.S) (O : Interface.S) : sig ... endmodule Private : sig ... end