Module `Hardcaml.Cyclesim`Source

Cycle accurate simulator

Sourcemodule Port_list : sig ... end

Sourcemodule Digest : sig ... end

Sourcemodule Config : sig ... end

Sourcetype ('i, 'o) t

base type of the cycle based simulators

Sourcetype t_port_list = (Port_list.t, Port_list.t) t

Sourceval circuit : (_, _) t -> Circuit.t Base.option

returns the circuit used to compile the simulation.

Sourceval cycle : (_, _) t -> Base.unit

advance by 1 clock cycle (check->comb->seq->comb)

Sourceval cycle_check : (_, _) t -> Base.unit

check inputs are valid before a simulation cycle

Sourceval cycle_before_clock_edge : (_, _) t -> Base.unit

update combinatorial logic before clock edge and relative to new inputs.

Sourceval cycle_at_clock_edge : (_, _) t -> Base.unit

update sequential logic - registers and memories.

Sourceval cycle_after_clock_edge : (_, _) t -> Base.unit

update combinatorial logic after clock edge

Sourceval reset : (_, _) t -> Base.unit

reset simulator

Sourceval in_port : (_, _) t -> Base.string -> Bits.t Base.ref

get input port given a name

Sourceval out_port : ?clock_edge:Side.t -> (_, _) t -> Base.string -> Bits.t Base.ref

Get output port given a name. If clock_edge is Before the outputs are computed prior to the clock edge - After means the outputs are computed after the clock edge.

Sourceval inputs : ('i, _) t -> 'i

Sourceval outputs : ?clock_edge:Side.t -> (_, 'o) t -> 'o

Sourceval in_ports : (_, _) t -> Port_list.t

Sourceval out_ports : ?clock_edge:Side.t -> (_, _) t -> Port_list.t

Sourceval internal_ports : (_, _) t -> Port_list.t

get list of internal nodes

Sourceval digest : (_, _) t -> Digest.t Base.ref

Sourceval lookup_signal : (_, _) t -> Signal.Uid.t -> Bits.t Base.ref

Sourceval lookup_reg : (_, _) t -> Signal.Uid.t -> Bits.t Base.ref

Sourcemodule Violated_or_not : sig ... end

Source

val results_of_assertions : 
  (_, _) t ->
  Violated_or_not.t Base.Map.M(Base.String).t

Sourceval create : ?config:Config.t -> Circuit.t -> t_port_list

construct a simulator from a circuit

Sourcemodule Combine_error : sig ... end

Source

val combine : 
  ?port_sets_may_differ:Base.bool ->
  ?on_error:(Combine_error.t -> Base.unit) ->
  ('i, 'o) t ->
  ('i, 'o) t ->
  ('i, 'o) t

Combine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and on_error is called if a difference is found. By default, on_error raises.

The simulators should have the same input and output port sets, unless port_sets_may_differ is true, in which case only ports which exist on both simulators are checked.

Sourcemodule With_interface (I : Interface.S) (O : Interface.S) : sig ... end

Sourcemodule Private : sig ... end

package hardcaml

Module Hardcaml.CyclesimSource

Module `Hardcaml.Cyclesim`Source