package hardcaml

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package hardcaml
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Module Hardcaml.SignalSource

Hardware design datatype suitable for simulation and netlist generation

Sourcetype signal_op =
  1. | Signal_add
  2. | Signal_sub
  3. | Signal_mulu
  4. | Signal_muls
  5. | Signal_and
  6. | Signal_or
  7. | Signal_xor
  8. | Signal_eq
  9. | Signal_lt

simple operators

Sourceval sexp_of_signal_op : signal_op -> Sexplib0.Sexp.t
Sourceval compare_signal_op : signal_op -> signal_op -> Base.int
Sourcemodule Uid : sig ... end
Sourcemodule Uid_set : sig ... end
Sourcemodule Uid_map : sig ... end
Sourcetype signal_id = {
  1. s_id : Uid.t;
  2. mutable s_names : Base.string Base.list;
  3. s_width : Base.int;
  4. mutable s_attributes : Rtl_attribute.t Base.list;
    (*

    Making this mutable turns hardcaml from pretty functional to pretty imperative. however, if used carefully and only with the library, we can provide a potentially easier way of changing the graph structure in some cases

    *)
  5. mutable s_deps : t Base.list;
  6. caller_id : Caller_id.t Base.option;
}

internal structure for tracking signals

Sourceand t =
  1. | Empty
  2. | Const of {
    1. signal_id : signal_id;
    2. constant : Bits.t;
    }
  3. | Op2 of {
    1. signal_id : signal_id;
    2. op : signal_op;
    3. arg_a : t;
    4. arg_b : t;
    }
  4. | Mux of {
    1. signal_id : signal_id;
    2. select : t;
    3. cases : t Base.list;
    }
  5. | Cat of {
    1. signal_id : signal_id;
    2. args : t Base.list;
    }
  6. | Not of {
    1. signal_id : signal_id;
    2. arg : t;
    }
  7. | Wire of {
    1. signal_id : signal_id;
    2. driver : t Base.ref;
    }
  8. | Select of {
    1. signal_id : signal_id;
    2. arg : t;
    3. high : Base.int;
    4. low : Base.int;
    }
  9. | Reg of {
    1. signal_id : signal_id;
    2. register : register;
    3. d : t;
    }
  10. | Mem of {
    1. signal_id : signal_id;
    2. extra_uid : Uid.t;
    3. register : register;
    4. memory : memory;
    }
  11. | Multiport_mem of {
    1. signal_id : signal_id;
    2. size : Base.int;
    3. write_ports : write_port Base.array;
    }
  12. | Mem_read_port of {
    1. signal_id : signal_id;
    2. memory : t;
    3. read_address : t;
    }
  13. | Inst of {
    1. signal_id : signal_id;
    2. extra_uid : Uid.t;
    3. instantiation : instantiation;
    }

main signal data type

Sourceand write_port = {
  1. write_clock : t;
  2. write_address : t;
  3. write_enable : t;
  4. write_data : t;
}
Sourceand read_port = {
  1. read_clock : t;
  2. read_address : t;
  3. read_enable : t;
}
Sourceand register = {
  1. reg_clock : t;
    (*

    clock

    *)
  2. reg_clock_edge : Edge.t;
    (*

    active clock edge

    *)
  3. reg_reset : t;
    (*

    asynchronous reset

    *)
  4. reg_reset_edge : Edge.t;
    (*

    asynchronous reset edge

    *)
  5. reg_reset_value : t;
    (*

    asychhronous reset value

    *)
  6. reg_clear : t;
    (*

    synchronous clear

    *)
  7. reg_clear_level : Level.t;
    (*

    synchronous clear level

    *)
  8. reg_clear_value : t;
    (*

    sychhronous clear value

    *)
  9. reg_enable : t;
    (*

    global system enable

    *)
}

These types are used to define a particular type of register as per the following template, where each part is optional:

 always @(?edge clock, ?edge reset)
   if (reset == reset_level) d <= reset_value;
   else if (clear == clear_level) d <= clear_value;
   else if (enable) d <= ...;
Sourceand memory = {
  1. mem_size : Base.int;
  2. mem_read_address : t;
  3. mem_write_address : t;
  4. mem_write_data : t;
}
Sourceand instantiation = {
  1. inst_name : Base.string;
    (*

    name of circuit

    *)
  2. inst_instance : Base.string;
    (*

    instantiation label

    *)
  3. inst_generics : Parameter.t Base.list;
    (*

    Parameter.int ...

    *)
  4. inst_inputs : (Base.string * t) Base.list;
    (*

    name and input signal

    *)
  5. inst_outputs : (Base.string * (Base.int * Base.int)) Base.list;
    (*

    name, width and low index of output

    *)
  6. inst_lib : Base.string;
  7. inst_arch : Base.string;
}
Sourcetype signal = t
Sourceval signal_id : t -> signal_id Base.option

returns the (private) signal_id. For internal use only.

Sourceval uid : t -> Uid.t

returns the unique id of the signal

Sourceval deps : t -> t Base.list

returns the signal's dependencies

returns the list of names assigned to the signal

Sourceval add_attribute : t -> Rtl_attribute.t -> t

Add an attribute to node. This is currently supported only in Verilog.

Sourceval attributes : t -> Rtl_attribute.t Base.list

Returns attributes associated to the signal

Sourceval has_name : t -> Base.bool
Sourceval is_reg : t -> Base.bool

is the signal a register?

Sourceval is_mem : t -> Base.bool

is the signal a memory, or multiport memory?

Sourceval is_multiport_mem : t -> Base.bool

is the signal a multiport memory?

Sourceval is_mem_read_port : t -> Base.bool

is the signal a memory read port?

Sourceval is_inst : t -> Base.bool

is the signal an instantiation?

Sourceval is_const : t -> Base.bool

is the signal a constant?

Sourceval is_select : t -> Base.bool

is the signal a part selection?

Sourceval is_wire : t -> Base.bool

is the signal a wire?

Sourceval is_op2 : signal_op -> t -> Base.bool

is the signal the given operator?

Sourceval is_cat : t -> Base.bool

is the signal concatenation?

Sourceval is_mux : t -> Base.bool

is the signal a multiplexer?

Sourceval is_not : t -> Base.bool

is the signal a not>

Sourceval const_value : t -> Bits.t

return the (binary) string representing a constants value

Sourceval new_id : Base.unit -> Uid.t

creates a new signal uid

Sourceval reset_id : Base.unit -> Base.unit

resets the signal identifiers

Sourceval make_id : Base.int -> t Base.list -> signal_id

constructs a signal_id type

Sourceval structural_compare : ?check_names:Base.bool -> ?check_deps:Base.bool -> ?initial_deps:Uid_set.t -> t -> t -> Uid_set.t * Base.bool

perform a recursive structural comparison of two signals

Sourceval sexp_of_signal_recursive : ?show_uids:Base.bool -> depth:Base.int -> t -> Base.Sexp.t

sexp_of_signal_recursive ~depth signal converts a signal recursively to a sexp for up to depth levels. If show_uids is false then signal identifiers will not be printed. max_list_length controls how many mux and concat arguments (dependancies) are printed.

Combinatorial signal API. This API automatically performs constant propogations (eg: replacing (a + 1 + 5) with (a + 6)). This reduces the amount of work that needs to be done during simulation by simply reducing the number of simulation nodes.

To use raw signals, ie: keeping the simulation nodes as described, use Raw below.

include Comb.S with type t := t
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
include Base.Equal.S with type t := t
Sourceval empty : t

the empty signal

Sourceval is_empty : t -> Base.bool
Sourceval (--) : t -> Base.string -> t

names a signal

let a = a -- "a" in ...

signals may have multiple names.

Sourceval width : t -> Base.int

returns the width (number of bits) of a signal.

let w = width s in ...

Sourceval address_bits_for : Base.int -> Base.int

addess_bits_for num_elements returns the address width required to index num_elements.

It is the same as Int.ceil_log2, except it wll return a minimum value of 1 (since you cannot have 0 width vectors). Raises if num_elements is < 0.

Sourceval num_bits_to_represent : Base.int -> Base.int

num_bits_to_represent x returns the number of bits required to represent the number x, which should be >= 0.

Sourceval of_constant : Constant.t -> t
Sourceval to_constant : t -> Constant.t
Sourceval constb : Base.string -> t

convert binary string to constant

Sourceval of_bit_string : Base.string -> t
Sourceval of_int : width:Base.int -> Base.int -> t

convert integer to constant

Sourceval of_int32 : width:Base.int -> Base.int32 -> t
Sourceval of_int64 : width:Base.int -> Base.int64 -> t
Sourceval of_hex : ?signedness:Constant.Signedness.t -> width:Base.int -> Base.string -> t

convert hex string to a constant. If the target width is greater than the hex length and signedness is Signed then the result is sign extended. Otherwise the result is zero padded.

Sourceval of_octal : ?signedness:Constant.Signedness.t -> width:Base.int -> Base.string -> t

convert octal string to a constant. If the target width is greater than the octal length and signedness is Signed then the result is sign extended. Otherwise the result is zero padded.

Sourceval of_z : width:Base.int -> Z.t -> t

Convert an arbitrarily wide integer value to a constant.

Sourceval of_string : Base.string -> t

convert verilog style or binary string to constant

Sourceval of_bit_list : Base.int Base.list -> t

convert IntbitsList to constant

Sourceval of_decimal_string : width:Base.int -> Base.string -> t
Sourceval of_char : Base.char -> t

convert a char to an 8 bit constant

Sourceval of_bool : Base.bool -> t

convert a bool to vdd or gnd

Sourceval to_z : t -> signedness:Constant.Signedness.t -> Z.t

Convert bits to a Zarith.t

Sourceval constv : Base.string -> t
  • deprecated [since 2019-11] constv]
Sourceval consti : width:Base.int -> Base.int -> t
  • deprecated [since 2019-11] consti]
Sourceval consti32 : width:Base.int -> Base.int32 -> t
  • deprecated [since 2019-11] consti32]
Sourceval consti64 : width:Base.int -> Base.int64 -> t
  • deprecated [since 2019-11] consti64]
Sourceval constibl : Base.int Base.list -> t
  • deprecated [since 2019-11] constibl]
Sourceval consthu : width:Base.int -> Base.string -> t
  • deprecated [since 2019-11] consthu]
Sourceval consths : width:Base.int -> Base.string -> t
  • deprecated [since 2019-11] consths]
Sourceval const : Base.string -> t
  • deprecated [since 2019-11] const
Sourceval constd : width:Base.int -> Base.string -> t
  • deprecated [since 2019-11] constd]
Sourceval concat_msb : t Base.list -> t

concat ts concatenates a list of signals - the msb of the head of the list will become the msb of the result.

let c = concat [ a; b; c ] in ...

concat raises if ts is empty or if any t in ts is empty.

Sourceval concat_lsb : t Base.list -> t

Similar to concat_msb except the lsb of the head of the list will become the lsb of the result.

Sourceval concat_msb_e : t Base.list -> t

same as concat_msb except empty signals are first filtered out

Sourceval concat_lsb_e : t Base.list -> t

same as concat_lsb except empty signals are first filtered out

Sourceval (@:) : t -> t -> t

concatenate two signals.

let c = a @: b in ...

equivalent to concat [ a; b ]

Sourceval vdd : t

logic 1

Sourceval is_vdd : t -> Base.bool
Sourceval gnd : t

logic 0

Sourceval is_gnd : t -> Base.bool
Sourceval zero : Base.int -> t

zero w makes a the zero valued constant of width w

Sourceval ones : Base.int -> t

ones w makes a constant of all ones of width w

Sourceval one : Base.int -> t

one w makes a one valued constant of width w

Sourceval select : t -> Base.int -> Base.int -> t

select t hi lo selects from t bits in the range hi...lo, inclusive. select raises unless hi and lo fall within 0 .. width t - 1 and hi >= lo.

Sourceval select_e : t -> Base.int -> Base.int -> t

same as select except invalid indices return empty

Sourceval bit : t -> Base.int -> t

select a single bit

Sourceval msb : t -> t

get most significant bit

Sourceval lsbs : t -> t

get least significant bits

Sourceval lsb : t -> t

get least significant bit

Sourceval msbs : t -> t

get most significant bits

Sourceval drop_bottom : t -> Base.int -> t

drop_bottom s n drop bottom n bits of s

Sourceval drop_top : t -> Base.int -> t

drop_top s n drop top n bits of s

Sourceval sel_bottom : t -> Base.int -> t

sel_bottom s n select bottom n bits of s

Sourceval sel_top : t -> Base.int -> t

sel_top s n select top n bits of s

Sourceval (.:[]) : t -> (Base.int * Base.int) -> t

x.:[hi, lo] == select x hi lo

Sourceval (.:+[]) : t -> (Base.int * Base.int Base.option) -> t

x.:+[lo, width] == select x (lo + width - 1) lo. If width is None it selects all remaining msbs of the vector ie x.:+[lo,None] == drop_bottom x lo

Sourceval (.:-[]) : t -> (Base.int Base.option * Base.int) -> t

x.:-[hi, width] == select x hi (hi - width + 1). If hi is None it defaults to the msb of the vector ie x.:-[None, width] == sel_top x width

Sourceval (.:()) : t -> Base.int -> t

x.(i) == bit x i

Sourceval insert : into:t -> t -> at_offset:Base.int -> t

insert ~into:t x ~at_offset insert x into t at given offet

Sourceval mux : t -> t Base.list -> t

multiplexer.

let m = mux sel inputs in ...

Given l = List.length inputs and w = width sel the following conditions must hold.

l <= 2**w, l >= 2

If l < 2**w, the last input is repeated.

All inputs provided must have the same width, which will in turn be equal to the width of m.

Sourceval mux2 : t -> t -> t -> t

mux2 c t f 2 input multiplexer. Selects t if c is high otherwise f.

t and f must have same width and c must be 1 bit.

Equivalent to mux c [f; t]

Sourceval mux_init : t -> Base.int -> f:(Base.int -> t) -> t
Sourceval (&:) : t -> t -> t

logical and

Sourceval (&:.) : t -> Base.int -> t
Sourceval (&&:) : t -> t -> t

a <>:. 0 &: b <>:. 0

Sourceval (|:) : t -> t -> t

logical or

Sourceval (|:.) : t -> Base.int -> t
Sourceval (||:) : t -> t -> t

a <>:. 0 |: b <>:. 0

Sourceval (^:) : t -> t -> t

logic xor

Sourceval (^:.) : t -> Base.int -> t
Sourceval (~:) : t -> t

logical not

Sourceval (+:) : t -> t -> t

addition

Sourceval (+:.) : t -> Base.int -> t
Sourceval (-:) : t -> t -> t

subtraction

Sourceval (-:.) : t -> Base.int -> t
Sourceval negate : t -> t

negation

Sourceval (*:) : t -> t -> t

unsigned multiplication

Sourceval (*+) : t -> t -> t

signed multiplication

Sourceval (==:) : t -> t -> t

equality

Sourceval (==:.) : t -> Base.int -> t
Sourceval (<>:) : t -> t -> t

inequality

Sourceval (<>:.) : t -> Base.int -> t
Sourceval (<:) : t -> t -> t

less than

Sourceval (<:.) : t -> Base.int -> t
Sourceval lt : t -> t -> t
Sourceval (>:) : t -> t -> t

greater than

Sourceval (>:.) : t -> Base.int -> t
Sourceval (<=:) : t -> t -> t

less than or equal to

Sourceval (<=:.) : t -> Base.int -> t
Sourceval (>=:) : t -> t -> t

greater than or equal to

Sourceval (>=:.) : t -> Base.int -> t
Sourceval (<+) : t -> t -> t

signed less than

Sourceval (<+.) : t -> Base.int -> t
Sourceval (>+) : t -> t -> t

signed greater than

Sourceval (>+.) : t -> Base.int -> t
Sourceval (<=+) : t -> t -> t

signed less than or equal to

Sourceval (<=+.) : t -> Base.int -> t
Sourceval (>=+) : t -> t -> t

signed greated than or equal to

Sourceval (>=+.) : t -> Base.int -> t
Sourceval (-->:) : t -> t -> t

Propositional logic implication operator

Sourceval to_string : t -> Base.string

create string from signal

Sourceval to_int : t -> Base.int

to_int t treats t as unsigned and resizes it to fit exactly within an OCaml Int.t.

  • If width t > Int.num_bits then the upper bits are truncated.
  • If width t >= Int.num_bits and bit t (Int.num_bits-1) = vdd (i.e. the msb of the resulting Int.t is set), then the result is negative.
  • If t is Signal.t and not a constant value, an exception is raised.
Sourceval to_sint : t -> Base.int

to_sint t treats t as signed and resizes it to fit exactly within an OCaml Int.t.

  • If width t > Int.num_bits then the upper bits are truncated.
  • If t is Signal.t and not a constant value, an exception is raised.
Sourceval to_int32 : t -> Base.int32
Sourceval to_sint32 : t -> Base.int32
Sourceval to_int64 : t -> Base.int64
Sourceval to_sint64 : t -> Base.int64
Sourceval to_bool : t -> Base.bool
Sourceval to_char : t -> Base.char

Convert signal to a char. The signal must be 8 bits wide.

Sourceval to_bstr : t -> Base.string

create binary string from signal

Sourceval bits_msb : t -> t Base.list

convert signal to a list of bits with msb at head of list

Sourceval bits_lsb : t -> t Base.list

convert signal to a list of bits with lsb at head of list

Sourceval to_array : t -> t Base.array

to_array s convert signal s to array of bits with lsb at index 0

Sourceval of_array : t Base.array -> t

of_array a convert array a of bits to signal with lsb at index 0

Sourceval repeat : t -> Base.int -> t

repeat signal n times

Sourceval split_in_half_msb : t -> t * t

split signal in half. The most significant bits will be in the left half of the returned tuple.

Sourceval split_lsb : ?exact:Base.bool -> part_width:Base.int -> t -> t Base.list

Split signal into a list of signals with width equal to part_width. The least significant bits are at the head of the returned list. If exact is true the input signal width must be exactly divisable by part_width. When exact is false and the input signal width is not exactly divisible by part_width, the last element will contains residual bits.

eg:

  split_lsb ~part_width:4 16b0001_0010_0011_0100 =
    [ 4b0100; 4b0011; 4b0010; 4b0001 ]

  split_lsb ~exact:false ~part_width:4 17b11_0001_0010_0011_0100 =
    [ 4b0100; 4b0011; 4b0010; 4b0001; 2b11 ]
Sourceval split_msb : ?exact:Base.bool -> part_width:Base.int -> t -> t Base.list

Like split_lsb except the most significant bits are at the head of the returned list. Residual bits when exact is false goes to the last element of the list, so in the general case split_lsb is not necessarily equivalent to split_msb |> List.rev.

Sourceval bswap : t -> t
Sourceval sll : t -> Base.int -> t

shift left logical

Sourceval srl : t -> Base.int -> t

shift right logical

Sourceval sra : t -> Base.int -> t

shift right arithmetic

Sourceval rotl : t -> Base.int -> t

rotate left

Sourceval rotr : t -> Base.int -> t

rotate right

Sourceval log_shift : (t -> Base.int -> t) -> t -> t -> t

shift by variable amount

Sourceval uresize : t -> Base.int -> t

uresize t w returns the unsigned resize of t to width w. If w = width t, this is a no-op. If w < width t, this selects the w low bits of t. If w > width t, this extends t with zero (width t - w).

Sourceval sresize : t -> Base.int -> t

sresize t w returns the signed resize of t to width w. If w = width t, this is a no-op. If w < width t, this selects the w low bits of t. If w > width t, this extends t with width t - w copies of msb t.

Sourceval ue : t -> t

unsigned resize by +1 bit

Sourceval se : t -> t

signed resize by +1 bit

Sourceval resize_list : resize:(t -> Base.int -> t) -> t Base.list -> t Base.list

resize_list ?resize l finds the maximum width in l and applies resize el max to each element.

Sourceval resize_op2 : resize:(t -> Base.int -> t) -> (t -> t -> t) -> t -> t -> t

resize_op2 ~resize f a b applies resize x w to a and b where w is the maximum of their widths. It then returns f a b

Sourceval reduce : f:('a -> 'a -> 'a) -> 'a Base.list -> 'a

fold 'op' though list

Sourceval reverse : t -> t

reverse bits

Sourceval mod_counter : max:Base.int -> t -> t

mod_counter max t is if t = max then 0 else (t + 1), and can be used to count from 0 to (max-1) then from zero again. If max == 1<<n, then a comparator is not generated and overflow arithmetic used instead. If

Sourceval compute_arity : steps:Base.int -> Base.int -> Base.int

compute_arity ~steps num_values computes the tree arity required to reduce num_values in steps. steps<=0 raises.

Sourceval compute_tree_branches : steps:Base.int -> Base.int -> Base.int Base.list

compute_tree_branches ~steps num_values returns a list of length steps of branching factors required to reduce num_values. This tends to produce a slightly more balanced sequence than just applying compute_arity at every step.

Sourceval tree : arity:Base.int -> f:('a Base.list -> 'a) -> 'a Base.list -> 'a

tree ~arity ~f input creates a tree of operations. The arity of the operator is configurable. tree raises if input = [].

Sourceval priority_select : ?branching_factor:Base.int -> (t, t) Hardcaml__.Comb_intf.with_valid2 Base.list -> (t, t) Hardcaml__.Comb_intf.with_valid2

priority_select cases returns the value associated with the first case whose valid signal is high. valid will be set low in the returned with_valid if no case is selected.

Sourceval priority_select_with_default : ?branching_factor:Base.int -> (t, t) Hardcaml__.Comb_intf.with_valid2 Base.list -> default:t -> t

Same as priority_select except returns default if no case matches.

Sourceval onehot_select : ?branching_factor:Base.int -> (t, t) Hardcaml__.Comb_intf.with_valid2 Base.list -> t

Select a case where one and only one valid signal is enabled. If more than one case is valid then the return value is undefined. If no cases are valid, 0 is returned by the current implementation, though this should not be relied upon.

Sourceval popcount : ?branching_factor:Base.int -> t -> t

popcount t returns the number of bits set in t.

Sourceval is_pow2 : ?branching_factor:Base.int -> t -> t

is_pow2 t returns a bit to indicate if t is a power of 2.

Sourceval leading_ones : ?branching_factor:Base.int -> t -> t

leading_ones t returns the number of consecutive 1s from the most significant bit of t down.

Sourceval trailing_ones : ?branching_factor:Base.int -> t -> t

trailing_ones t returns the number of consecutive 1s from the least significant bit of t up.

Sourceval leading_zeros : ?branching_factor:Base.int -> t -> t

leading_zeros t returns the number of consecutive 0s from the most significant bit of t down.

Sourceval trailing_zeros : ?branching_factor:Base.int -> t -> t

trailing_zeros t returns the number of consecutive 0s from the least significant bit of t up.

Sourceval floor_log2 : ?branching_factor:Base.int -> t -> (t, t) Hardcaml__.Comb_intf.with_valid2

floor_log2 x returns the floor of log-base-2 of x. x is treated as unsigned and an error is indicated by valid = gnd in the return value if x = 0.

Sourceval ceil_log2 : ?branching_factor:Base.int -> t -> (t, t) Hardcaml__.Comb_intf.with_valid2

ceil_log2 x returns the ceiling of log-base-2 of x. x is treated as unsigned and an error is indicated by valid = gnd in the return value if x = 0.

Sourceval binary_to_onehot : t -> t

convert binary to onehot

Sourceval onehot_to_binary : t -> t

convert onehot to binary

Sourceval binary_to_gray : t -> t

convert binary to gray code

Sourceval gray_to_binary : t -> t

convert gray code to binary

Sourceval random : width:Base.int -> t

create random constant vector of given width

Sourcemodule type TypedMath = sig ... end
Sourcemodule Uop : TypedMath with type v := t

Unsigned operations compatible with type t

Sourcemodule Sop : TypedMath with type v := t

Signed operations compatible with type t

Sourceval wire : Base.int -> t

creates an unassigned wire

Sourceval wireof : t -> t

creates an assigned wire

Sourceval (<==) : t -> t -> Base.unit

assigns to wire

Sourceval assign : t -> t -> Base.unit
Sourceval input : Base.string -> Base.int -> t

creates an input

Sourceval output : Base.string -> t -> t

creates an output

Sourcemodule Unoptimized : Comb.S with type t = t

Comb logic API without constant propogation optimizations.

Sourcemodule Reg_spec_ : sig ... end

Reg_spec_ is a register specification. It is named Reg_spec_ rather than Reg_spec so that people consistently use the name Hardcaml.Reg_spec rather than Hardcaml.Signal.Reg_spec_.

Sourceval reg : Reg_spec_.t -> ?enable:t -> t -> t
Sourceval reg_fb : ?enable:t -> Reg_spec_.t -> width:Base.int -> f:(t -> t) -> t
Sourceval pipeline : ?attributes:Rtl_attribute.t Base.list -> Reg_spec_.t -> n:Base.int -> ?enable:t -> t -> t

Pipeline a signal n times with the given register specification. If set, a list of RTL attributes will also be applied to each register created.

Sourceval memory : Base.int -> write_port:write_port -> read_address:t -> t
Sourceval ram_wbr : ?attributes:Rtl_attribute.t Base.list -> write_port:write_port -> read_port:read_port -> Base.int -> t
Sourceval ram_rbw : ?attributes:Rtl_attribute.t Base.list -> write_port:write_port -> read_port:read_port -> Base.int -> t
Sourceval multiport_memory : ?name:Base.string -> ?attributes:Rtl_attribute.t Base.list -> Base.int -> write_ports:write_port Base.array -> read_addresses:t Base.array -> t Base.array

Pretty printer.

OCaml

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