Synchronous FIFO implementions with optional showahead functionality and pipelining stages.
include sig ... endval sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.tval iter : 'a t -> f:('a -> Base.unit) -> Base.unitval to_list : 'a t -> 'a Base.listval t : (Base.string * Base.int) tval equal : 'a Base__Equal.equal -> 'a t Base__Equal.equalval port_names : Base.string tval port_widths : Base.int tval to_alist : 'a t -> (Base.string * 'a) Base.listval of_alist : (Base.string * 'a) Base.list -> 'a tval fold : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc) -> 'accval offsets : ?rev:Base.bool -> Base.unit -> Base.int tmodule type Comb = sig ... endmodule Of_bits : sig ... endmodule Of_signal : sig ... endmodule Of_always : sig ... endmodule Names_and_widths : sig ... endtype 'a create_params =
?nearly_empty:Base.int ->
?nearly_full:Base.int ->
?overflow_check:Base.bool ->
?reset:Signal.t ->
?underflow_check:Base.bool ->
?ram_attributes:Rtl_attribute.t Base.list ->
?scope:Scope.t ->
'amodule Kinded_fifo : sig ... endval create :
?showahead:Base.bool ->
?nearly_empty:Base.int ->
?nearly_full:Base.int ->
?overflow_check:Base.bool ->
?reset:Signal.t ->
?underflow_check:Base.bool ->
?ram_attributes:Rtl_attribute.t Base.list ->
?scope:Scope.t ->
Base.unit ->
capacity:Base.int ->
clock:Signal.t ->
clear:Signal.t ->
wr:Signal.t ->
d:Signal.t ->
rd:Signal.t ->
Signal.t Hardcaml__.Fifo_intf.T.tcreate ~clock ~clear ~wr ~d ~rd capacity builds a FIFO with capacity elements which is written with d when wr is high and read when rd is high.
The default reset configuration is to use a synchronous clr signal. An asynchronous rst may be optionally provided. One of clr or rst must be non-empty.
Optional overflow and underflow checking may be used. Data will not be written(/read) when the fifo is full(/empty) regardles or the wr/(rd) signals.
nearly_emtpy and nearly_full may be programmed to go high when the fifo is nearing an underflow or overflow state.
The showahead mode changes the read behaviour of the FIFO. When showahead is false read data is available 1 cycle after rd is high. With showahead true the data is available on the same cycle as rd is high. To support showahead behaviour the timing of the full/empty flag also changes (although they still correctly indicate when it is safe to read or write to the FIFO). showahead mode has some extra cost in terms of extra logic. The implementation ensures the output is registered and timing performance is good - nearly as fast as the underlying RAM allows..
Note; showahead is sometimes referred to as "first word fall through". It uses the write-before-read ram mode which is problematic in synthesis so we include special logic that performs collision detection.
The used output indicates the number of elements currently in the FIFO.
val showahead_fifo_of_classic_fifo :
Kinded_fifo.create_classic ->
Kinded_fifo.create_showahead Base.Staged.tval create_classic_with_extra_reg :
?nearly_empty:Base.int ->
?nearly_full:Base.int ->
?overflow_check:Base.bool ->
?reset:Signal.t ->
?underflow_check:Base.bool ->
?ram_attributes:Rtl_attribute.t Base.list ->
?scope:Scope.t ->
Base.unit ->
capacity:Base.int ->
clock:Signal.t ->
clear:Signal.t ->
wr:Signal.t ->
d:Signal.t ->
rd:Signal.t ->
Signal.t Hardcaml__.Fifo_intf.T.tAdds an extra output register to the non-showahead fifo. This delays the output, but ensures there is no logic data on the fifo output. Adds an extra cycle of latency (2 cycles from write to empty low).
val create_showahead_from_classic : create_fifoConstructs a showahead fifo from a non-showahead fifo. Only modifies the control flags. Has 2 cycles of latency.
val create_showahead_with_extra_reg : create_fifoConstructs a fifo similarly to create_showahead_from_classic and ensures the output data is registered. Has 3 cycles of latency, but is slightly faster than create
~showahead:true - it seems to only be limited by the underlying RAM frequency.
module type Config = sig ... endmodule With_interface (Config : Config) : sig ... endCreate FIFO using interfaces.