package hardcaml

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package hardcaml
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Module Hardcaml.VcdSource

VCD (Verilog Change Dump) generation

Sourceval wrap : (string -> unit) -> ('i, 'o) Cyclesim.t -> ('i, 'o) Cyclesim.t

wrap a simulator to generate a vcd file

Sourcemodule Gtkwave : sig ... end

Drive the gtkwave waveform viewer