9-state VHDL std_logic enumeration
include Ppx_compare_lib.Comparable.S with type t := tval compare : t Base__Ppx_compare_lib.compareinclude Ppx_enumerate_lib.Enumerable.S with type t := tval all : t listval sexp_of_t : t -> Sexplib0.Sexp.tval u : tval x : tval l0 : tval l1 : tval z : tval w : tval l : tval h : tval don't_care : tval is_u : t -> Base.boolval is_x : t -> Base.boolval is_l0 : t -> Base.boolval is_l1 : t -> Base.boolval is_z : t -> Base.boolval is_w : t -> Base.boolval is_l : t -> Base.boolval is_h : t -> Base.boolval is_don't_care : t -> Base.boolval u_val : t -> Base.unit Base.optionval x_val : t -> Base.unit Base.optionval l0_val : t -> Base.unit Base.optionval l1_val : t -> Base.unit Base.optionval z_val : t -> Base.unit Base.optionval w_val : t -> Base.unit Base.optionval l_val : t -> Base.unit Base.optionval h_val : t -> Base.unit Base.optionval don't_care_val : t -> Base.unit Base.optionmodule Variants : sig ... endinclude Base.Equal.S with type t := tval equal : t Base__Equal.equalval to_int : t -> Base.intProvide the index of t in textual order. When passing a std_logic parameter from verilog to vhdl, we need to encode this type into an integer. For example, L1 = 4'd3.
val of_char_exn : Base.char -> tThe OCaml char used in of_char and to_char is the same as used in VHDL.
val to_char : t -> Base.char