package hardcaml

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Module
Module type
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Class type
module type S = sig ... end
module LutEqn : sig ... end

Allow expressions to generate LUT init values

module Hardcaml_api : S

Hardcaml simulation based models of Xilinx primitives

module Unisim : S

Unisim library based Xilinx primitives

module type T = sig ... end
module type LutSize = sig ... end
module Lut4 : LutSize
module Lut6 : LutSize
module XMake (X : S) (L : LutSize) : T
module XComb (Synth : T) : Comb.Primitives with type t = Signal.t

combinatorial only transform

sequential and combinatorial transform TODO memories