package hardcaml

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package hardcaml

hardcaml
- CHANGES
- LICENSE
- README
- Library hardcaml
  - Hardcaml
    
    Always
    
    Variable
    
    Fields
    
    Direct
    
    State_machine
    
    Encoding
    
    State
    
    Bits
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Mutable
    
    Comb
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Caller_id
    
    Mode
    
    Circuit
    
    Signal_map
    
    Create_options
    
    Port_checks
    
    With_interface
    
    Circuit_database
    
    Comb
    
    Gates
    
    Primitives
    
    S
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Make_primitives
    
    Make
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Combinational_op
    
    Combinational_ops_database
    
    Constant
    
    Signedness
    
    Bit
    
    Make_bit_list
    
    Cosim
    
    Comms
    
    With_interface
    
    Cosim2
    
    Comms
    
    Simulator
    
    Icarus
    
    Mti32
    
    Mti64
    
    Make
    
    With_interface
    
    Cyclesim
    
    Port_list
    
    Combine_error
    
    With_interface
    
    Private
    
    Step
    
    Cyclesim_float_ops
    
    Real
    
    Float
    
    Double
    
    Edge
    
    Fifo
    
    Fixed
    
    Make
    
    Round
    
    Overflow
    
    Fixed
    
    Unsigned
    
    Round
    
    Overflow
    
    Spec
    
    Make
    
    Signed
    
    Round
    
    Overflow
    
    Spec
    
    Make
    
    Graph
    
    Hierarchy
    
    With_interface
    
    In_scope
    
    IntbitsList
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Interface
    
    Pre
    
    S
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Ast
    
    Ast
    
    Field
    
    Type
    
    Sequence
    
    Kind
    
    Empty
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Ast
    
    Ast
    
    Field
    
    Type
    
    Sequence
    
    Kind
    
    Empty
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    S_with_ast
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Create_fn
    
    Make
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Instantiation
    
    With_interface
    
    Level
    
    Mangler
    
    Parameter
    
    Std_logic
    
    Variants
    
    Unstable
    
    Std_logic_vector
    
    Unstable
    
    Bit_vector
    
    Unstable
    
    Value
    
    Variants
    
    Unstable
    
    Unstable
    
    Parameter_name
    
    Ram
    
    Collision_mode
    
    Write_port
    
    Read_port
    
    Recipe
    
    Monad
    
    Same
    
    Same
    
    SVar
    
    SList
    
    SArray
    
    STuple2
    
    STuple3
    
    Reg_spec
    
    Reserved_words
    
    Rtl
    
    Language
    
    Output_mode
    
    Rtl_attribute
    
    Value
    
    Vivado
    
    Scope
    
    Path
    
    Naming_scheme
    
    Side
    
    Signal
    
    Uid
    
    Uid_map
    
    Uid_set
    
    Const_prop
    
    Comb
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Reg_spec_
    
    Signal_graph
    
    Structural
    
    Config
    
    Base
    
    Base0
    
    Base1
    
    Base2
    
    Lib
    
    Transform
    
    TransformFn'
    
    TransformFn
    
    MakePureCombTransform_arg
    
    MakePureCombTransform
    
    MakeCombTransform
    
    CopyTransform
    
    Vcd
    
    Gtkwave
    
    With_valid
    
    Xilinx
    
    S
    
    LutEqn
    
    Hardcaml_api
    
    Unisim
    
    T
    
    LutSize
    
    Lut4
    
    Lut6
    
    XMake
    
    XComb
    
    XSynthesizeComb
    
    XSynthesize
- Sources
  - hardcaml
    
    always.ml
    
    bits.ml
    
    bits0.ml
    
    bits_intf.ml
    
    caller_id.ml
    
    circuit.ml
    
    circuit_database.ml
    
    comb.ml
    
    comb_intf.ml
    
    combinational_op.ml
    
    combinational_ops_database.ml
    
    constant.ml
    
    cosim.ml
    
    cosim2.ml
    
    cosim2_intf.ml
    
    cyclesim.ml
    
    cyclesim_float_ops.ml
    
    cyclesim_float_ops_intf.ml
    
    cyclesim_intf.ml
    
    edge.ml
    
    fifo.ml
    
    fixed.ml
    
    fixed_intf.ml
    
    graph.ml
    
    hardcaml.ml
    
    hardcaml__.ml
    
    hierarchy.ml
    
    import.ml
    
    instantiation.ml
    
    intbitsList.ml
    
    interface.ml
    
    interface_intf.ml
    
    level.ml
    
    mangler.ml
    
    map.ml
    
    map_intf.ml
    
    parameter.ml
    
    parameter_name.ml
    
    ram.ml
    
    recipe.ml
    
    recipe_intf.ml
    
    reg_spec.ml
    
    reserved_words.ml
    
    rtl.ml
    
    rtl_attribute.ml
    
    rtl_intf.ml
    
    scope.ml
    
    side.ml
    
    signal.ml
    
    signal_graph.ml
    
    signal_intf.ml
    
    structural.ml
    
    structural_intf.ml
    
    transform.ml
    
    transform_intf.ml
    
    vcd.ml
    
    with_valid.ml
    
    xilinx.ml
    
    xilinx_intf.ml
    
    zarith.ml

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Module `Signal.Const_prop`

module Comb : Comb.S with type t := t