package hardcaml

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package hardcaml
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Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

if and switch control constructs are provided. ($==) is used for assignment.

Code is written as lists of assignments, if and control statements.

variables;

let var = wire (zero 8) in
let var = reg r_sync enable 8 in

assignment;

var $== exp;

if statements;

if_ condition [ ... ] [ ... ]

switch statements;

switch condition [
  consti 3 0 [ ... ];
  consti 3 1 [ ... ];
  consti 3 2 [ ... ];
  consti 3 3 [ ... ];
]

signals;

let (s:signal) = q (v:guarded) in

compilation;

compile [ ... ]

example;

      let state = reg r_sync enable 2 in
      let a = wire 8 in
      compile [
        if_ a#q ==: consti 8 4 [
          a $== consti 8 2
        ] [
          switch (q state) [
          (consti 2 0) [
            a $==. 3;
            state $== const 2 1;
          ];
          (consti 2 1) [
            a $==. 2;
            state $== const 2 2;
          ];
          (consti 2 2) [
            a $==. 1;
            state $== const 2 3;
          ];
          (consti 2 3) [
            a $==. 0;
            state $== const 2 4;
          ]
        ]
      ];
      let state = state#q in
      let a = a#q in
      ....
type t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
type always = t
module Variable : sig ... end

The type of variables in guarded assignments. Variables may be asychronous wires, or synchronous regs. The current value of the variable may be accessed through the value field below.

type 'a case = 'a * t Base.List.t
type 'a cases = 'a case Base.List.t
val if_ : Signal.t -> t Base.List.t -> t Base.List.t -> t

if statement

else if branch

val when_ : Signal.t -> t Base.List.t -> t

if sel then ... else

val unless : Signal.t -> t Base.List.t -> t

if sel then else ...

val switch : Signal.t -> Signal.t cases -> t

switch statement

val proc : t Base.List.t -> t

Allows sequences of expressions to be inserted into the code; a syntactic nicety.

val (<--) : Variable.t -> Signal.t -> t

assignment

val (<--.) : Variable.t -> Base.Int.t -> t

assignment with an integer constant - width is inferred

module State_machine : sig ... end
val compile : t Base.List.t -> Base.Unit.t

compile to structural code