hardcaml v0.12.0 · OCaml Package

Icarus Verilog Cosimulation interface

type delta_message = {

sets : (Base.String.t * Base.String.t) Base.List.t;
gets : Base.String.t Base.List.t;
delta_time : Base.Int64.t;

}

run sets, then gets then schedule next callback at cur_time+delta_time

type init_message = Base.String.t Base.List.t

expected inputs and outputs

type control_message =

| Finish
| Run of delta_message

control message

type response_message = (Base.String.t * Base.String.t) Base.List.t

response message

val net_addr : Base.String.t

val net_port : Base.Int.t

module Comms : sig ... end

basic TCP communications between client (simulation) and server (hardcaml)

val control : Unix.file_descr -> control_message -> response_message

send a control message to the simulation

val write_testbench : 
  ?dump_file:Base.String.t ->
  name:Base.String.t ->
  inputs:(Base.String.t * Base.Int.t) Base.List.t ->
  outputs:(Base.String.t * Base.Int.t) Base.List.t ->
  (Base.String.t -> Base.Unit.t) ->
  Base.Unit.t

write test harness

val write_testbench_from_circuit : 
  ?dump_file:Base.String.t ->
  (Base.String.t -> Base.Unit.t) ->
  Circuit.t ->
  Base.Unit.t

write test hardness derivied from a hardcaml circuit

val compile : Base.String.t Base.List.t -> Base.String.t -> Base.Unit.t

compile verilog files to a vvp simulation object

val derive_clocks_and_resets : 
  Circuit.t ->
  Base.String.t Base.List.t * Base.String.t Base.List.t

find clocks and resets in a hardcaml circuit

val load_sim : Base.String.t -> Base.Unit.t

load vvp file into simulator along with vpi object

val compile_and_load_sim : ?dump_file:Base.String.t -> Circuit.t -> Base.Unit.t

compile circuit and load simulation

val init_sim : 
  (Base.Unit.t -> Base.Unit.t) ->
  (Base.String.t * Base.Int.t) Base.List.t ->
  (Base.String.t * Base.Int.t) Base.List.t ->
  Unix.file_descr

val make_sim_obj : 
  server:Unix.file_descr ->
  clocks:(Base.String.t * Base.Int.t) Base.List.t ->
  resets:(Base.String.t * Base.Int.t) Base.List.t ->
  inputs:(Base.String.t * Base.Int.t) Base.List.t ->
  outputs:(Base.String.t * Base.Int.t) Base.List.t ->
  Cyclesim.t_port_list

val make : ?dump_file:Base.String.t -> Circuit.t -> Cyclesim.t_port_list

create simulator from hardcaml circuit

val load : 
  clocks:(Base.String.t * Base.Int.t) Base.List.t ->
  resets:(Base.String.t * Base.Int.t) Base.List.t ->
  inputs:(Base.String.t * Base.Int.t) Base.List.t ->
  outputs:(Base.String.t * Base.Int.t) Base.List.t ->
  Base.String.t ->
  Cyclesim.t_port_list

load icarus vvp simulation

module With_interface (I : Interface.S) (O : Interface.S) : sig ... end

package hardcaml