module Path : sig ... endmodule Naming_scheme : sig ... endControl of name generation in a hierarchy of modules. The position of a module within a hierarchy is determined by a path which leads back to the (single) top most parent module. Signal names may be pre-pended with some represtation of that path.
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.tval create :
?flatten_design:Base.Bool.t ->
?naming_scheme:Naming_scheme.t ->
?name:Base.String.t ->
Base.Unit.t ->
tcreate ?flatten_design ?naming_scheme ?name () creates a new scope. If flatten_design is true, then all module instantions are inlined. Names for wires are determiend by naming_scheme.
val sub_scope : t -> Base.String.t -> tsub_scope t label returns a new scope with label appended to its hierarchical path
path t returns the Path.t associated with t. This will determine the prefix used when naming modules that are associated with this scope.
val circuit_database : t -> Circuit_database.tcircuit_database t returns the circuit database associated with t. Note that circuit databases are shared among sub_scopes.
val flatten_design : t -> Base.Bool.tflatten_design t returns true when HardCaml will inline all module instantiations.
val naming_scheme : t -> Naming_scheme.tnaming_scheme t returns the Naming.t that t was constructed with.
val naming : ?sep:Base.String.t -> t -> Signal.t -> Base.String.t -> Signal.tnaming ?sep t signal name assigns a heirarchical name to signal based on the path of t and name. sep, when provided, determines the separator for path components in the heirarchical name.
This is typically used as a partial application to construct a new signal naming operator, .e.g:
let (--) = naming scope in
(* ... other code ... *)
let named_signal = some_signal -- "data" in
(* ... more code ... *)