package hardcaml

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package hardcaml
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Parameters

module X : Pre

Signature

val sexp_of_t : ('a -> Ppx_sexp_conv_lib.Sexp.t) -> 'a X.t -> Ppx_sexp_conv_lib.Sexp.t
val iter : 'a X.t -> f:('a -> Base.Unit.t) -> Base.Unit.t
val iter2 : 'a X.t -> 'b X.t -> f:('a -> 'b -> Base.Unit.t) -> Base.Unit.t
val map : 'a X.t -> f:('a -> 'b) -> 'b X.t
val map2 : 'a X.t -> 'b X.t -> f:('a -> 'b -> 'c) -> 'c X.t
val to_list : 'a X.t -> 'a Base.List.t
include Base.Equal.S1 with type 'a t := 'a X.t
val port_names : Base.String.t X.t

RTL names specified in the interface definition - commonly also the OCaml field name.

val port_widths : Base.Int.t X.t

Bit widths specified in the interface definition.

val to_alist : 'a X.t -> (Base.String.t * 'a) Base.List.t

Create association list indexed by field names.

val of_alist : (Base.String.t * 'a) Base.List.t -> 'a X.t

Create interface from association list indexed by field names

val zip : 'a X.t -> 'b X.t -> ('a * 'b) X.t
val zip3 : 'a X.t -> 'b X.t -> 'c X.t -> ('a * 'b * 'c) X.t
val zip4 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> ('a * 'b * 'c * 'd) X.t
val zip5 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> 'e X.t -> ('a * 'b * 'c * 'd * 'e) X.t
val map3 : 'a X.t -> 'b X.t -> 'c X.t -> f:('a -> 'b -> 'c -> 'd) -> 'd X.t
val map4 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> f:('a -> 'b -> 'c -> 'd -> 'e) -> 'e X.t
val map5 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> 'e X.t -> f:('a -> 'b -> 'c -> 'd -> 'e -> 'f) -> 'f X.t
val iter3 : 'a X.t -> 'b X.t -> 'c X.t -> f:('a -> 'b -> 'c -> Base.Unit.t) -> Base.Unit.t
val iter4 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> f:('a -> 'b -> 'c -> 'd -> Base.Unit.t) -> Base.Unit.t
val iter5 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> 'e X.t -> f:('a -> 'b -> 'c -> 'd -> 'e -> Base.Unit.t) -> Base.Unit.t
val fold : 'a X.t -> init:'b -> f:('b -> 'a -> 'b) -> 'b
val fold2 : 'a X.t -> 'b X.t -> init:'c -> f:('c -> 'a -> 'b -> 'c) -> 'c
val offsets : ?rev:Base.Bool.t -> Base.Unit.t -> Base.Int.t X.t

Offset of each field within the interface. The first field is placed at the least significant bit, unless the rev argument is true.

val of_interface_list : 'a X.t Base.List.t -> 'a Base.List.t X.t

Take a list of interfaces and produce a single interface where each field is a list.

val to_interface_list : 'a Base.List.t X.t -> 'a X.t Base.List.t

Create a list of interfaces from a single interface where each field is a list. Raises if all lists don't have the same length.

module type Comb = sig ... end
module Make_comb (Comb : Comb.S) : Comb with type comb = Comb.t
module Of_bits : Comb with type comb = Bits.t
module Of_signal : sig ... end