package hardcaml

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package hardcaml
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9-state VHDL std_logic enumeration

type t =
  1. | U
    (*

    Uninitialized

    *)
  2. | X
    (*

    Unknown

    *)
  3. | L0
    (*

    Logic 0

    *)
  4. | L1
    (*

    Logic 1

    *)
  5. | Z
    (*

    High impedance

    *)
  6. | W
    (*

    Weak - neither prefer 0 or 1

    *)
  7. | L
    (*

    Weak - prefer 0

    *)
  8. | H
    (*

    Weak - prefer 1

    *)
  9. | Don't_care
    (*

    Dont care

    *)
val compare : t -> t -> Base.Int.t
val all : t Base.List.t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val u : t
val x : t
val l0 : t
val l1 : t
val z : t
val w : t
val l : t
val h : t
val don't_care : t
module Variants : sig ... end
include Base.Equal.S with type t := t
val equal : t Base.Equal.equal
module Unstable : sig ... end
val to_int : t -> Base.Int.t

Provide the index of t in textual order. When passing a std_logic parameter from verilog to vhdl, we need to encode this type into an integer. For example, L1 = 4'd3.

val of_char_exn : Base.Char.t -> t

The OCaml char used in of_char and to_char is the same as used in VHDL.

val to_char : t -> Base.Char.t