package hardcaml_of_verilog

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in-package search v0.2.0

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Parameters
Signature

hardcaml_of_verilog
- Hardcaml_of_verilog
  - Circuit_to_json
  - Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    V
    
    Bit
    
    Cell
    
    V
    
    Connection
    
    V
    
    Direction
    
    Int_or_string
    
    Module
    
    V
    
    Netname
    
    V
    
    Parameter
    
    V
    
    Port
    
    V
    
    Port_direction
    
    V
  - Netlist
    
    Bit
    
    Bus
    
    Bus_names
    
    Cell
    
    Module
    
    Parameter
    
    Port
    
    Fields
    
    Direct
  - Ocaml_module
    
    Rebuild_interfaces
    
    X
  - Pass
  - Verilog_circuit
  - Verilog_design
    
    Crunched
    
    Define
    
    Define_value
    
    Defines
    
    Embedded_files
    
    Module
    
    Parameter
    
    Parameters
  - With_interface
    
    Make

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Parameter
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Parameters

module I : Hardcaml.Interface.S

module O : Hardcaml.Interface.S

Signature

val create : 
  ?verbose:Base.bool ->
  ?passes:Pass.t Base.list ->
  Verilog_design.t ->
  (Hardcaml.Signal.t I.t ->
    Hardcaml.Signal.t O.t Base.Or_error.t)
    Base.Or_error.t