hardcaml_of_verilog
  1. Overview
  2. Docs
Convert Verilog to a Hardcaml design

Install

github.com Readme MIT License Edit opam file

Authors

  1. J
    Jane Street Group, LLC

Maintainers

  1. J
    Jane Street developers

Sources

hardcaml_of_verilog-v0.15.0.tar.gz
sha256=2548df37bf5dae8a61f6042e2bb1120272697b1b331707f9989d267890c3ee0d

Description

The opensource synthesis tool yosys is used to convert a verilog design to a JSON based netlist representation. This library can load the JSON netlist and build a hardcaml circuit.

Code can also be generated to wrap the conversion process using Hardcaml interfaces.

Published: 21 Mar 2022

Dependencies (10)

  1. dune >= "2.0.0"
  2. stdio >= "v0.15" & < "v0.16"
  3. ppx_jsonaf_conv >= "v0.15" & < "v0.16"
  4. ppx_jane >= "v0.15" & < "v0.16"
  5. ppx_deriving_hardcaml >= "v0.15" & < "v0.16"
  6. jsonaf >= "v0.15" & < "v0.16"
  7. hardcaml >= "v0.15" & < "v0.16"
  8. core_unix >= "v0.15" & < "v0.16"
  9. base >= "v0.15" & < "v0.16"
  10. ocaml >= "4.08.0"

Dev Dependencies

None

Used by

None

Conflicts

None