package hardcaml_of_verilog

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Parameters

module I : Hardcaml.Interface.S
module O : Hardcaml.Interface.S
module X : sig ... end

Signature

val verilog_design : Verilog_design.t
module I : Hardcaml.Interface.S with type 'a t = 'a I.t
module O : Hardcaml.Interface.S with type 'a t = 'a O.t
val create : Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t
val inst : ?name:Base.string -> ?instance:Base.string -> Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t
val hierarchical : ?name:Base.string -> ?instance:Base.string -> Hardcaml.Scope.t -> Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t
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