package hardcaml_of_verilog

You can search for identifiers within the package.

in-package search v0.2.0

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Iterators

hardcaml_of_verilog
- Hardcaml_of_verilog
  - Circuit_to_json
  - Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    V
    
    Bit
    
    Cell
    
    V
    
    Connection
    
    V
    
    Direction
    
    Int_or_string
    
    Module
    
    V
    
    Netname
    
    V
    
    Parameter
    
    V
    
    Port
    
    V
    
    Port_direction
    
    V
  - Netlist
    
    Bit
    
    Bus
    
    Bus_names
    
    Cell
    
    Module
    
    Parameter
    
    Port
    
    Fields
    
    Direct
  - Ocaml_module
    
    Rebuild_interfaces
    
    X
  - Pass
  - Verilog_circuit
  - Verilog_design
    
    Crunched
    
    Define
    
    Define_value
    
    Defines
    
    Embedded_files
    
    Module
    
    Parameter
    
    Parameters
  - With_interface
    
    Make

Legend:
Library
Module
Module type
Parameter
Class
Class type

type t

include Sexplib0.Sexpable.S with type t := t

val t_of_sexp : Sexplib0__.Sexp.t -> t

val sexp_of_t : t -> Sexplib0__.Sexp.t

val create : 
  ?blackbox:Base.bool ->
  ?parameters:Parameters.t ->
  ?instantiates:t Base.list ->
  module_name:Base.string ->
  path:Base.string ->
  Base.unit ->
  t

val override : 
  ?module_name:Base.string ->
  ?path:Base.string ->
  ?instantiates:t Base.list ->
  ?parameters:Parameters.t ->
  ?blackbox:Base.bool ->
  t ->
  t

val blackbox : t -> Base.bool

val parameters : t -> Parameters.t

val module_name : t -> Base.string

val path : t -> Base.string

val instantiates : t -> t Base.list

Iterators

Depth first and call f from the leaves towards the root of the hierarchy.

val iter : t -> f:(t -> Base.unit) -> Base.unit

val map : t -> f:(t -> t) -> t

val flat_map : t -> f:(t -> 'a) -> 'a Base.list

Convert to a list. The "top" of the design is at the head of the list.