package hardcaml_of_verilog

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package hardcaml_of_verilog
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Module Verilog_design.ModuleSource

Sourcetype t
include Sexplib0.Sexpable.S with type t := t
Sourceval t_of_sexp : Sexplib0.Sexp.t -> t
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
Sourceval create : ?blackbox:Base.bool -> ?parameters:Parameters.t -> ?instantiates:t Base.list -> module_name:Base.string -> path:Base.string -> Base.unit -> t
Sourceval override : ?module_name:Base.string -> ?path:Base.string -> ?instantiates:t Base.list -> ?parameters:Parameters.t -> ?blackbox:Base.bool -> t -> t
Sourceval blackbox : t -> Base.bool
Sourceval parameters : t -> Parameters.t
Sourceval module_name : t -> Base.string
Sourceval path : t -> Base.string
Sourceval instantiates : t -> t Base.list

Iterators

Depth first and call f from the leaves towards the root of the hierarchy.

Sourceval iter : t -> f:(t -> Base.unit) -> Base.unit
Sourceval map : t -> f:(t -> t) -> t
Sourceval flat_map : t -> f:(t -> 'a) -> 'a Base.list

Convert to a list. The "top" of the design is at the head of the list.

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