package hardcaml_of_verilog

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type t = Parameter.t Base.list
include Sexplib0.Sexpable.S with type t := t
val t_of_sexp : Sexplib0__.Sexp.t -> t
val sexp_of_t : t -> Sexplib0__.Sexp.t
val replace : t -> with_:t -> t
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