diffast-langs-verilog 0.1.1 (latest)

module Loc = Diffast_misc.Loc

module Astml = Diffast_core.Astml

module Lang_base = Diffast_core.Lang_base

module Spec = Diffast_core.Spec

module Charpool = Diffast_core.Charpool

module Ast = Verilog_parsing.Ast

module Labels = Verilog_parsing.Labels

module Label = Verilog_parsing.Label

module Ls = Labels

type identifier = string

val lang_prefix : string

val keyroot_depth_min : int

type tie_id = Lang_base.tie_id

val null_tid : string * string

val mktid : 'a -> 'b -> 'a * 'b

val tid_to_string : (string * string) -> string

val anonymize_tid : ?more:bool -> Lang_base.tie_id -> string * string

val mktidattr : Lang_base.tie_id -> (string * string) list

module type T = sig ... end

val conv_loc : Ast.Loc.t -> Loc.t

module OverloadOperator : sig ... end

module AssignmentOperator : sig ... end

module IncOrDecOperator : sig ... end

module UnaryOperator : sig ... end

module BinaryOperator : sig ... end

module TimingCheck : sig ... end

module SystemTask : sig ... end

module Qualifier : sig ... end

module NetType : sig ... end

module PortDirection : sig ... end

module Gate : sig ... end

module DataType : sig ... end

module Expression : sig ... end

module EventExpression : sig ... end

module PropertyExpression : sig ... end

module SequenceExpression : sig ... end

module JoinSpec : sig ... end

module Statement : sig ... end

module CompilerDirective : sig ... end

module Strength : sig ... end

module SimpleImmediateAssertion : sig ... end

module DeferredImmediateAssertion : sig ... end

module ConcurrentAssertion : sig ... end

module ModuleSpec : sig ... end

module AlwaysSpec : sig ... end

module BinsSpec : sig ... end

type annotation = string option

val null_annotation : 'a option

val annotation_to_string : string option -> string

include module type of struct include Label end

type t = Verilog_parsing.Label.t =

| Dummy
| Error
| Empty
| SourceText
| LibraryText
| CompilerDirective of Verilog_parsing.Labels.CompilerDirective.t
| ModuleDeclaration of Verilog_parsing.Labels.ModuleSpec.t * Verilog_parsing.Common.identifier
| UdpDeclaration of Verilog_parsing.Common.identifier
| NetDeclaration of Verilog_parsing.Common.identifier list
| BindDirective of Verilog_parsing.Common.identifier
| Expr of Verilog_parsing.Labels.Expression.t
| Stmt of Verilog_parsing.Labels.Statement.t
| NetType of Verilog_parsing.Labels.NetType.t
| LocalParameterDeclaration of Verilog_parsing.Common.identifier list
| ParameterDeclaration of Verilog_parsing.Common.identifier list
| ParameterPortDeclaration
| ModuleBody
| Instantiation of Verilog_parsing.Common.identifier
| GateInstantiation of Verilog_parsing.Labels.Gate.t
| ContinuousAssign
| Assign
| ConcurrentAssertionItem
| DeferredImmediateAssertionItem
| PpIdentifier of Verilog_parsing.Common.identifier
| PackedDimension
| ParamAssignment of Verilog_parsing.Common.identifier
| DefparamAssignment
| IdSelect of Verilog_parsing.Common.identifier
| Select
| Range
| RangePlus
| RangeMinus
| RangeForeach
| Root
| This
| Super
| Cellpin of Verilog_parsing.Common.identifier
| CellpinStar
| CellpinAnon
| DelayValue of Verilog_parsing.Common.identifier
| PackageScope of Verilog_parsing.Common.identifier
| PackageScopeUnit
| PackageScopeLocal
| PackageImport of Verilog_parsing.Common.identifier
| PackageImportAny
| LifetimeStatic
| LifetimeAutomatic
| EndLabel of Verilog_parsing.Common.identifier
| EndLabelNew
| ClassType of Verilog_parsing.Common.identifier
| DataType of Verilog_parsing.Labels.DataType.t
| ImplicitDataType
| VarDeclAssignments
| Signed
| Unsigned
| ArgsDotted of Verilog_parsing.Common.identifier
| Tagged
| StructUnionBody
| StructUnionMember
| ClassScopeId of Verilog_parsing.Common.identifier
| Void
| EnumNameDeclaration of Verilog_parsing.Common.identifier
| EnumBody
| IdClassSel of Verilog_parsing.Common.identifier
| Variable of Verilog_parsing.Common.identifier
| Extern
| PackageImportDeclaration
| PackageImportItem of Verilog_parsing.Common.identifier
| Packed
| ParameterValueAssignment
| Ports
| PortsStar
| BitSelect
| VariableDeclAssignment of Verilog_parsing.Common.identifier
| DynamicArrayNew
| VariableDimension
| VariableDimensionStar
| GenItemBegin
| GenBlockId of Verilog_parsing.Common.identifier
| GenerateRegion
| Scalared
| Vectored
| DelayControl
| NetSig of Verilog_parsing.Common.identifier
| ParameterOverride
| PortDeclaration
| PortDirection of Verilog_parsing.Labels.PortDirection.t
| Strength of Verilog_parsing.Labels.Strength.t
| StrengthSupply0
| StrengthSupply1
| StrengthSpec
| VarDataType
| Port of Verilog_parsing.Common.identifier
| InterfacePort of Verilog_parsing.Common.identifier
| InterfacePortInterface
| ModportIdentifier of Verilog_parsing.Common.identifier
| PortMulti
| ExprScope
| ExprScopeThis
| ExprScopeSuper
| ExprScopeDot
| ExprScopeDotSuper
| CondPredicate
| CondPattern
| Dist
| DistItem
| DistWeight
| DistWeightRange
| ArrayRange
| ArrayRangePlus
| ArrayRangeMinus
| CastingTypeSimple
| CastingTypeSigned
| CastingTypeUnsigned
| CastingTypeString
| CastingTypeConst
| ValueRange
| Pattern
| PatternId of Verilog_parsing.Common.identifier
| PatternStar
| PatternTagged of Verilog_parsing.Common.identifier
| EventControl
| EventControlStar
| EventControlParenStar
| EventControlRepeat
| EvExpr of Verilog_parsing.Labels.EventExpression.t
| CaseItem
| CaseItemDefault
| CaseInsideItem
| CaseInsideItemDefault
| CaseItems
| CaseItemsMatches
| CaseItemsInside
| With
| Args
| ConstraintBlock
| ForInit
| ForInitItemDT of Verilog_parsing.Common.identifier
| ForInitItemLval
| StreamingConcat
| OrderRL
| OrderLR
| StreamConcat
| Solve
| SolveBefore
| ActionBlock
| CycleDelay of string
| CycleDelayId of Verilog_parsing.Common.identifier
| CycleDelayParen
| Priority
| Unique
| Unique0
| InstRange
| InstName of Verilog_parsing.Common.identifier
| PExpr of Verilog_parsing.Labels.PropertyExpression.t
| ClockingEvent of Verilog_parsing.Common.identifier
| ClockingEventParen
| PropertyCase
| PropertyCaseDefault
| DisableIff
| CycleDelayRange of string
| CycleDelayRangeId of Verilog_parsing.Common.identifier
| CycleDelayRangeParen
| CycleDelayRangeBracket
| CycleDelayRangeBracketStar
| CycleDelayRangeBracketPlus
| SExpr of Verilog_parsing.Labels.SequenceExpression.t
| ConsecutiveRepetition
| NonconsecutiveRepetition
| GotoRepetition
| NetAlias
| InitialConstruct
| FinalConstruct
| AlwaysConstruct of Verilog_parsing.Labels.AlwaysSpec.t
| ConcurrentAssertionItemLabeled of Verilog_parsing.Common.identifier
| ConcurrentAssertionStmt of Verilog_parsing.Labels.ConcurrentAssertion.t
| DeferredImmediateAssertionItemLabeled of Verilog_parsing.Common.identifier
| DeferredImmediateAssertionStmt of Verilog_parsing.Labels.DeferredImmediateAssertion.t
| SimpleImmediateAssertionStmt of Verilog_parsing.Labels.SimpleImmediateAssertion.t
| CheckerInstantiation of Verilog_parsing.Common.identifier
| LoopGenerateConstruct
| GenvarDeclaration of Verilog_parsing.Common.identifier list
| GenvarIterationAssign of Verilog_parsing.Labels.AssignmentOperator.t * Verilog_parsing.Common.identifier
| GenvarIterationIncOrDec of Verilog_parsing.Labels.IncOrDecOperator.t * Verilog_parsing.Common.identifier
| GenvarIdDecl of Verilog_parsing.Common.identifier
| GenvarInitId of Verilog_parsing.Common.identifier
| GenvarInit
| SpecifyBlock
| SpecparamDeclaration
| SpecparamAssignmentId of Verilog_parsing.Common.identifier
| SpecparamAssignmentPulseControl of Verilog_parsing.Common.identifier
| PulsestyleDeclarationOnevent
| PulsestyleDeclarationOndetect
| ShowcancelledDeclaration
| NoshowcancelledDeclaration
| SpecifyTerminalDescriptor
| InputOrOutputId of Verilog_parsing.Common.identifier
| InterfaceIdentifier of Verilog_parsing.Common.identifier
| ProgramDeclaration of Verilog_parsing.Common.identifier
| InterfaceDeclaration of Verilog_parsing.Common.identifier
| InterfaceDeclarationExtern of Verilog_parsing.Common.identifier
| TimeUnitsDeclaration
| TimeUnit of string
| Timeprecision of string
| PackageDeclaration of Verilog_parsing.Common.identifier
| AnonymousProgram
| AnonymousProgramItemEmpty
| FunctionDeclaration of Verilog_parsing.Common.identifier
| FunctionPrototype of Verilog_parsing.Common.identifier
| FuncId of Verilog_parsing.Common.identifier
| FuncIdVoid of Verilog_parsing.Common.identifier
| FuncIdNew
| TfIdScoped of Verilog_parsing.Common.identifier
| TaskDeclaration of Verilog_parsing.Common.identifier
| TaskPrototype of Verilog_parsing.Common.identifier
| ClassCtorPrototype
| TfPortListPart
| TfBody
| TfPortDeclaration
| TfPortItemAssignment of Verilog_parsing.Common.identifier
| TfPortItem
| TfVariableIdentifier of Verilog_parsing.Common.identifier
| CheckerDeclaration of Verilog_parsing.Common.identifier
| PropertyDeclaration of Verilog_parsing.Common.identifier
| PropertyDeclBody
| PropertyPortItem
| PropertyPortItemDir
| PropertyPortItemAssignment of Verilog_parsing.Common.identifier
| SequenceDeclaration of Verilog_parsing.Common.identifier
| SequenceDeclBody
| LetDeclaration of Verilog_parsing.Common.identifier
| PropertyStatementSpec
| AssertionVariableDeclaration
| SequenceFormalTypeSequence
| SequenceFormalTypeUntyped
| DataDeclarationVar
| Const
| DataDeclarationVarClass
| TypeDeclaration of Verilog_parsing.Common.identifier
| ScopedType of Verilog_parsing.Common.identifier
| TypeIdentifier of Verilog_parsing.Common.identifier
| TypeDeclEnum
| TypeDeclStruct
| TypeDeclUnion
| TypeDeclClass
| VirtualInterfaceDeclaration of Verilog_parsing.Common.identifier
| ModportDeclaration of Verilog_parsing.Common.identifier list
| ModportItem of Verilog_parsing.Common.identifier
| ModportSimplePortsDecl
| ModportClockingDecl of Verilog_parsing.Common.identifier
| ModportTfPortsDeclImport
| ModportTfPortsDeclExport
| ModportSimplePort of Verilog_parsing.Common.identifier
| ModportSimplePortDot of Verilog_parsing.Common.identifier
| ModportTfPort of Verilog_parsing.Common.identifier
| CovergroupDeclaration of Verilog_parsing.Common.identifier
| Paren
| CoverageOption of Verilog_parsing.Common.identifier * Verilog_parsing.Common.identifier
| CoverPoint
| CoverPointLabeled of Verilog_parsing.Common.identifier
| CoverCross
| CoverCrossLabeled of Verilog_parsing.Common.identifier
| CrossItem of Verilog_parsing.Common.identifier
| Iff
| BinsList
| BinsEmpty
| SelectBins
| SelectBinsEmpty
| Bins of Verilog_parsing.Labels.BinsSpec.t * Verilog_parsing.Common.identifier
| BinsSelection of Verilog_parsing.Labels.BinsSpec.t * Verilog_parsing.Common.identifier
| BinsExpressionVar of Verilog_parsing.Common.identifier
| BinsExpression of Verilog_parsing.Common.identifier * Verilog_parsing.Common.identifier
| NBins
| SelCondBinsof
| SelExprNot
| SelExprAnd
| SelExprOr
| SelExprParen
| Intersect
| Wildcard
| TransSet
| TransRangeList
| RepeatRange
| TransItem
| TransRepetitionConsecutive
| TransRepetitionNonconsecutive
| TransRepetitionGoto
| Default
| DefaultSequence
| OpenRangeList
| CoverageEventWith of Verilog_parsing.Common.identifier
| CoverageEventBlockEvent
| BlockEventExpression
| BlockEventExpressionBegin
| BlockEventExpressionEnd
| HierarchicalBtfIdentifier of Verilog_parsing.Common.identifier
| PackageExportDeclarationStar
| PackageExportDeclaration
| DpiImport of string
| DpiExportFunc of string * Verilog_parsing.Common.identifier
| DpiExportTask of string * Verilog_parsing.Common.identifier
| DpiImportLabel of Verilog_parsing.Common.identifier
| DpiTfImportPropertyContext
| DpiTfImportPropertyPure
| ExternConstraintDeclaration
| Static
| Virtual
| ClassDeclaration of Verilog_parsing.Common.identifier
| ClassExtends
| ClassItemEmpty
| ClassMethod
| Qualifier of Verilog_parsing.Labels.Qualifier.t
| ClassBody
| ClassConstraint of Verilog_parsing.Common.identifier
| Pure
| ClassProperty
| PackageOrGenerateItemEmpty
| Forkjoin
| ExternTfDeclaration of Verilog_parsing.Common.identifier
| TimingCheck of Verilog_parsing.Labels.TimingCheck.t
| SystemTimingCheck
| Notifier of Verilog_parsing.Common.identifier
| Delayed of Verilog_parsing.Common.identifier
| TimingCheckEvent
| TimingCheckEventControlPosedge
| TimingCheckEventControlNegedge
| TimingCheckEventControl
| EdgeDescriptor of string
| OverloadDeclaration of Verilog_parsing.Labels.OverloadOperator.t * Verilog_parsing.Common.identifier
| Params
| ClockingDeclaration of Verilog_parsing.Common.identifier
| Global
| ClockingBody
| ClockingItemDefault
| ClockingItem
| DefaultSkewInput
| DefaultSkewOutput
| DefaultSkewInputOutput
| ClockingDirectionInput
| ClockingDirectionInputOutput
| ClockingDirectionInout
| ClockingSkewPosedge
| ClockingSkewNegedge
| ClockingSkewEdge
| ClockingSkew
| ClockingDeclAssign of Verilog_parsing.Common.identifier
| Production of Verilog_parsing.Common.identifier
| ProductionItem of Verilog_parsing.Common.identifier
| RsCodeBlock
| RsRule
| RsProductionList
| RsProductionListRandJoin
| WeightSpecInt of string
| WeightSpecId
| WeightSpec
| RsProdIf
| RsProdRepeat
| RsProdCase
| RsCaseItem
| RsCaseItemDefault
| CheckerOrGenerateItemEmpty
| ConditionalGenerateConstructCase
| ConditionalGenerateConstructIf
| ElaborationSystemTask of Verilog_parsing.Labels.SystemTask.t
| CaseGenerateItem
| CaseGenerateItemDefault
| AssignmentPattern
| AssignmentPatternExpr
| PatternKey
| PatternKeyDefault
| PatternMember
| SimplePathDeclaration
| ParallelPathDescription
| FullPathDescription
| PathInputs
| PathOutputs
| PathDelayValue
| PolarityPlus
| PolarityMinus
| EdgePosedge
| EdgeNegedge
| EdgeSensitivePathDeclaration
| ParallelEdgeSensitivePathDescription
| FullEdgeSensitivePathDescription
| ParallelEdgeSensitivePathDescriptionSub
| FullEdgeSensitivePathDescriptionSub
| StateDependentPathDeclarationIf
| StateDependentPathDeclarationIfnone
| VariableLvalue
| AttributeInstance
| AttrSpec of Verilog_parsing.Common.identifier
| UdpPort of Verilog_parsing.Common.identifier
| UdpPortDeclaration
| UdpOutputDeclaration of Verilog_parsing.Common.identifier
| UdpOutputDeclarationReg of Verilog_parsing.Common.identifier
| UdpInputDeclaration
| UdpRegDeclaration of Verilog_parsing.Common.identifier
| SequentialBody
| CombinationalBody
| UdpInitialStmt of Verilog_parsing.Common.identifier * string
| SequentialEntry
| EdgeIndicator
| EdgeSymbol of string
| LevelSymbol of string
| OutputSymbol of string
| CombinationalEntry
| NextStateMinus
| UdpPortsStar
| UdpPorts
| UdpPortDecls
| UdpDeclarationPorts
| AttributeInstances
| ConfigDeclaration of Verilog_parsing.Common.identifier
| DesignStatement
| CellId of Verilog_parsing.Common.identifier
| LibraryIdentifier of Verilog_parsing.Common.identifier
| LiblistClause
| CellClause of Verilog_parsing.Common.identifier
| UseClause
| ColonConfig
| InstanceName
| InstanceIdentifier of Verilog_parsing.Common.identifier
| TopModuleIdentifier of Verilog_parsing.Common.identifier
| InstClause
| ConfigRuleStatementDefault
| ConfigRuleStatement
| LibraryDeclaration of Verilog_parsing.Common.identifier
| Incdir
| FilePathSpec of string
| IncludeStatement of string
| PragmaExpression of Verilog_parsing.Common.identifier
| PragmaValueTuple
| PragmaValueNum of string
| PragmaValueStr of string
| PragmaValueId of Verilog_parsing.Common.identifier
| PackageImportDecls
| ParamPorts
| Ranges
| VariableDimensions
| CaseConds
| NetDeclAssignments of Verilog_parsing.Common.identifier list
| ParamAssignments of Verilog_parsing.Common.identifier list
| MacroExpr of string
| MacroStmt of string
| Var

val to_string : t -> string

val to_simple_string : t -> Verilog_parsing.Common.identifier

val to_tag : 
  ?strip:bool ->
  t ->
  string * (string * Verilog_parsing.Common.identifier) list

val get_identifiers : t -> Verilog_parsing.Common.identifier list

val get_identifier : t -> Verilog_parsing.Common.identifier

val pexpr_to_stmt : t -> t

val expr_to_stmt : t -> t

val expr_of_integral_number : string -> t

val expr : Verilog_parsing.Labels.Expression.t -> t

val expr_uo : Verilog_parsing__Labels.UnaryOperator.t -> t

val expr_bo : Verilog_parsing__Labels.BinaryOperator.t -> t

val expr_ao : Verilog_parsing__Labels.AssignmentOperator.t -> t

val pexpr : Verilog_parsing.Labels.PropertyExpression.t -> t

val sexpr : Verilog_parsing.Labels.SequenceExpression.t -> t

val ev_expr : Verilog_parsing.Labels.EventExpression.t -> t

val stmt : Verilog_parsing.Labels.Statement.t -> t

val stmt_ao : Verilog_parsing__Labels.AssignmentOperator.t -> t

val sia_stmt : Verilog_parsing.Labels.SimpleImmediateAssertion.t -> t

val dia_stmt : Verilog_parsing.Labels.DeferredImmediateAssertion.t -> t

val ca_stmt : Verilog_parsing.Labels.ConcurrentAssertion.t -> t

val qualifier : Verilog_parsing.Labels.Qualifier.t -> t

val timing_check : Verilog_parsing.Labels.TimingCheck.t -> t

val data_type : Verilog_parsing.Labels.DataType.t -> t

val net_type : Verilog_parsing.Labels.NetType.t -> t

val compiler_directive : Verilog_parsing.Labels.CompilerDirective.t -> t

val is_error : t -> bool

val f : CompilerDirective.t -> CompilerDirective.t

val strip : 'a -> 'a

val anonymize : ?more:bool -> t -> t

val anonymize2 : t -> t

val anonymize3 : t -> t

val to_short_string : ?ignore_identifiers_flag:bool -> t -> string

val is_hunk_boundary : 'a -> 'b -> bool

val forced_to_be_collapsible : 'a -> bool

val is_collapse_target : < no_collapse_flag : bool.. > -> t -> bool

val is_to_be_notified : t -> bool

val is_boundary : t -> bool

val is_partition : t -> bool

val is_sequence : t -> bool

val is_ntuple : 'a -> bool

val get_category : t -> string

val get_name : ?strip:bool -> t -> Verilog_parsing.Common.identifier

val get_names : t -> Verilog_parsing.Common.identifier list

val get_value : t -> string

val has_value : t -> bool

val has_non_trivial_value : t -> bool

val has_non_trivial_tid : 'a -> bool

val is_compatible : ?weak:bool -> 'a -> 'b -> bool

val is_order_insensitive : 'a -> bool

val quasi_eq : 'a -> 'b -> bool

val relabel_allowed : (t * t) -> bool

val move_disallowed : 'a -> bool

val is_common : 'a -> bool

val get_ident_use : t -> Verilog_parsing.Common.identifier

val to_char : 'a -> char

val has_names : t -> bool

val has_a_name : t -> bool

val is_named : t -> bool

val is_named_orig : t -> bool

val to_elem_data : 
  ?strip:bool ->
  ?afilt:(string -> bool) ->
  Astml.Loc.t ->
  t ->
  string * (string * string) list * string

val of_elem_data : 'a -> 'b -> 'c -> t

val getlab : < data : < _label : Obj.t.. >.. > -> t

val cannot_be_keyroot : < data : < _label : Obj.t.. >.. > -> bool

val is_string_literal : 'a -> bool

val is_int_literal : 'a -> bool

val is_real_literal : 'a -> bool

val is_phantom : t -> bool

val is_special : 'a -> bool

val is_always_construct : t -> bool

val is_timing_control : t -> bool

val is_continuous_assign : t -> bool

val is_blocking_assign : t -> bool

val is_non_blocking_assign : t -> bool

val is_if : t -> bool

val is_case : t -> bool

val is_case_item : t -> bool

val is_case_cond : t -> bool

val is_module_decl : t -> bool

val is_ports : t -> bool

val is_port : t -> bool

val is_port_dir : t -> bool

val is_net_type : t -> bool

val is_data_type : t -> bool

val is_var_data_type : t -> bool

val is_signing : t -> bool

val is_ranges : t -> bool

val is_variable_dims : t -> bool

val is_inst : t -> bool

val is_initial_construct : t -> bool

val is_final_construct : t -> bool

val is_generate_region : t -> bool

val is_param_port_decl : t -> bool

val is_param_assign : t -> bool

val is_data_decl_var : t -> bool

val is_net_decl : t -> bool

val is_reg : t -> bool

val is_wire : t -> bool

val is_expr : t -> bool

val is_op : 'a -> bool

val is_scope_creating : 'a -> bool

val is_stmt : t -> bool

val is_statement : t -> bool

val is_primary : 'a -> bool

val is_block : 'a -> bool

val is_pp_define : t -> bool

val is_pp_include : t -> bool

val is_source_text : t -> bool

package diffast-langs-verilog