package diffast-langs-verilog

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include module type of struct include Ls.AssignmentOperator end
type t = Verilog_parsing.Labels.AssignmentOperator.t =
  1. | Eq
  2. | AddEq
  3. | SubtEq
  4. | MultEq
  5. | DivEq
  6. | ModEq
  7. | AndEq
  8. | OrEq
  9. | XorEq
  10. | ShiftLEq
  11. | ShiftREq
  12. | SShiftREq
val to_string : t -> string
val to_simple_string : t -> string
val to_tag : t -> string * 'a list
val to_tag_name : t -> string
val to_short_string : t -> string
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