package diffast-langs-verilog

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include module type of struct include Ls.AlwaysSpec end
type t = Verilog_parsing.Labels.AlwaysSpec.t =
  1. | NORMAL
  2. | COMB
  3. | FF
  4. | LATCH
val to_string : t -> string
val to_rep : t -> string
val to_short_string : t -> string
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