package diffast-langs-verilog

You can search for identifiers within the package.

in-package search v0.2.0

package diffast-langs-verilog

diffast-langs-verilog
- Mverilog
  - V_change
    
    F
    
    CB
    
    c
    
    L
    
    c
    
    change_set
  - V_lib
    
    Analyzing
    
    Postprocessing
    
    mid_data
    
    tree_comparator
    
    Change
    
    CB
    
    c
    
    F
    
    L
    
    c
    
    c
    
    change_set
    
    tree_builder
diffast-langs-verilog.base
- Verilog_base
  - V_fact
    
    F
    
    FB
    
    extractor_base
    
    L
    
    extractor
  - V_label
    
    AlwaysSpec
    
    AssignmentOperator
    
    BinaryOperator
    
    BinsSpec
    
    CompilerDirective
    
    ConcurrentAssertion
    
    DataType
    
    DeferredImmediateAssertion
    
    EventExpression
    
    Expression
    
    Gate
    
    IncOrDecOperator
    
    JoinSpec
    
    ModuleSpec
    
    NetType
    
    OverloadOperator
    
    PortDirection
    
    PropertyExpression
    
    Qualifier
    
    SequenceExpression
    
    SimpleImmediateAssertion
    
    Statement
    
    Strength
    
    SystemTask
    
    T
    
    TimingCheck
    
    UnaryOperator
  - V_lib_base
    
    Fact
    
    FB
    
    extractor_base
    
    extractor
    
    Tree
    
    c
    
    node_data
    
    node_maker
    
    ordinal_tbl
    
    tree_builder
  - V_tree
    
    Tree
    
    c
    
    node_data
    
    node_maker
    
    ordinal_tbl
  - V_unparsing
diffast-langs-verilog.p
- Mverilog_p
  - V_lib_p
    
    tree_builder

Legend:
Library
Module
Module type
Parameter
Class
Class type

include module type of struct include Ls.CompilerDirective end

type t = Verilog_parsing.Labels.CompilerDirective.t =

| Define of Verilog_parsing.Common.identifier
| Undef of Verilog_parsing.Common.identifier
| Undefineall
| Include of string
| SysInclude of string
| Timescale of string * string
| Error of string
| Line of string * string * string
| Resetall
| Default_nettypeNone
| Default_nettype
| Pragma of Verilog_parsing.Common.identifier
| Begin_keywords of string
| End_keywords
| Default_decay_time of string
| Default_trireg_strength of string
| Delay_mode_distributed
| Delay_mode_path
| Delay_mode_unit
| Delay_mode_zero
| Celldefine
| Endcelldefine
| Unconnected_drive
| Nounconnected_drive

val to_string : t -> string

val to_simple_string : t -> string

val get_name : t -> Verilog_parsing.Common.identifier

val to_tag : t -> string * (string * Verilog_parsing.Common.identifier) list

val anonymize : t -> t

val to_short_string : ?ignore_identifiers_flag:bool -> t -> string