package diffast-langs-verilog

You can search for identifiers within the package.

in-package search v0.2.0

Legend:
Library
Module
Module type
Parameter
Class
Class type

include module type of struct include Ls.Statement end

type t = Verilog_parsing.Labels.Statement.t =

| Empty
| OperatorAssignment of Verilog_parsing.Labels.AssignmentOperator.t
| Labeled of Verilog_parsing.Common.identifier
| BlockingAssignment
| NonBlockingAssignment
| Assign
| Deassign
| Force
| Release
| Case
| Casex
| Casez
| Conditional
| IncOrDec
| SubroutineCall
| SubroutineCallVoid
| Disable
| DisableFork
| EventTrigger
| EventTriggerNonBlocking
| Forever
| Repeat
| While
| For
| Do
| Foreach
| Return
| Break
| Continue
| ParBlock of Verilog_parsing.Common.identifier * Verilog_parsing.Labels.JoinSpec.t
| ProceduralTimingControl
| SeqBlock of Verilog_parsing.Common.identifier
| Wait
| WaitFork
| WaitOrder
| ProceduralAssertion
| ClockingDrive
| Randsequence of Verilog_parsing.Common.identifier
| Randcase
| ExpectProperty
| Expr of Verilog_parsing.Labels.Expression.t
| PExpr of Verilog_parsing.Labels.PropertyExpression.t

val to_string : t -> string

val get_name : t -> Verilog_parsing.Common.identifier

val to_simple_string : t -> Verilog_parsing.Common.identifier

val to_tag : t -> string * (string * Verilog_parsing.Common.identifier) list

val get_identifier : t -> Verilog_parsing.Common.identifier

val anonymize : t -> t

val to_short_string : ?ignore_identifiers_flag:bool -> t -> string