package diffast-langs-verilog

You can search for identifiers within the package.

in-package search v0.2.0

diffast-langs-verilog
- Mverilog
  - V_change
    
    F
    
    CB
    
    c
    
    L
    
    c
    
    change_set
  - V_lib
    
    Analyzing
    
    Postprocessing
    
    mid_data
    
    tree_comparator
    
    Change
    
    CB
    
    c
    
    F
    
    L
    
    c
    
    c
    
    change_set
    
    tree_builder
diffast-langs-verilog.base
- Verilog_base
  - V_fact
    
    F
    
    FB
    
    extractor_base
    
    L
    
    extractor
  - V_label
    
    AlwaysSpec
    
    AssignmentOperator
    
    BinaryOperator
    
    BinsSpec
    
    CompilerDirective
    
    ConcurrentAssertion
    
    DataType
    
    DeferredImmediateAssertion
    
    EventExpression
    
    Expression
    
    Gate
    
    IncOrDecOperator
    
    JoinSpec
    
    ModuleSpec
    
    NetType
    
    OverloadOperator
    
    PortDirection
    
    PropertyExpression
    
    Qualifier
    
    SequenceExpression
    
    SimpleImmediateAssertion
    
    Statement
    
    Strength
    
    SystemTask
    
    T
    
    TimingCheck
    
    UnaryOperator
  - V_lib_base
    
    Fact
    
    FB
    
    extractor_base
    
    extractor
    
    Tree
    
    c
    
    node_data
    
    node_maker
    
    ordinal_tbl
    
    tree_builder
  - V_tree
    
    Tree
    
    c
    
    node_data
    
    node_maker
    
    ordinal_tbl
  - V_unparsing
diffast-langs-verilog.p
- Mverilog_p
  - V_lib_p
    
    tree_builder

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include Verilog_base.V_label.Spec.LABEL_T

type annotation

val null_annotation : annotation

val annotation_to_string : annotation -> string

type t

val to_string : t -> string

val to_char : t -> char

val to_short_string : ?ignore_identifiers_flag:bool -> t -> string

val to_simple_string : t -> string

val to_elem_data : 
  ?strip:bool ->
  ?afilt:(string -> bool) ->
  Diffast_core.Spec.Loc.t ->
  t ->
  string * (string * string) list * string

val of_elem_data : string -> (string * string) list -> string -> t

val relabel_allowed : (t * t) -> bool

val quasi_eq : t -> t -> bool

val is_compatible : ?weak:bool -> t -> t -> bool

val is_order_insensitive : t -> bool

val move_disallowed : t -> bool

val is_common : t -> bool

val is_to_be_notified : t -> bool

val is_collapse_target : Diffast_core.Parser_options.c -> t -> bool

val is_hunk_boundary : t -> t -> bool

val forced_to_be_collapsible : t -> bool

val is_named : t -> bool

val is_named_orig : t -> bool

val keyroot_depth_min : int

val is_boundary : t -> bool

val is_partition : t -> bool

val is_sequence : t -> bool

val is_ntuple : t -> bool

val strip : t -> t

val anonymize : ?more:bool -> t -> t

val anonymize2 : t -> t

val anonymize3 : t -> t

val get_ident_use : t -> string

val get_category : t -> string

val get_name : ?strip:bool -> t -> string

val get_value : t -> string

val has_value : t -> bool

val has_non_trivial_value : t -> bool

val has_non_trivial_tid : t -> bool

val cannot_be_keyroot : Diffast_core.Spec.node_t -> bool

val is_phantom : t -> bool

val is_special : t -> bool

val is_string_literal : t -> bool

val is_int_literal : t -> bool

val is_real_literal : t -> bool

val is_statement : t -> bool

val is_block : t -> bool

val is_primary : t -> bool

val is_op : t -> bool

val is_scope_creating : t -> bool

val to_tag : ?strip:bool -> t -> string * (string * string) list

val lang_prefix : string

val is_always_construct : t -> bool

val is_timing_control : t -> bool

val is_continuous_assign : t -> bool

val is_blocking_assign : t -> bool

val is_non_blocking_assign : t -> bool

val is_if : t -> bool

val is_case : t -> bool

val is_case_item : t -> bool

val is_case_cond : t -> bool

val is_module_decl : t -> bool

val is_ports : t -> bool

val is_port : t -> bool

val is_port_dir : t -> bool

val is_net_type : t -> bool

val is_data_type : t -> bool

val is_var_data_type : t -> bool

val is_signing : t -> bool

val is_ranges : t -> bool

val is_variable_dims : t -> bool

val is_inst : t -> bool

val is_initial_construct : t -> bool

val is_final_construct : t -> bool

val is_generate_region : t -> bool

val is_param_port_decl : t -> bool

val is_param_assign : t -> bool

val is_data_decl_var : t -> bool

val is_net_decl : t -> bool

val is_reg : t -> bool

val is_wire : t -> bool

val is_expr : t -> bool

val is_stmt : t -> bool

val is_pp_define : t -> bool

val is_pp_include : t -> bool

val is_source_text : t -> bool

val getlab : Verilog_base.V_label.Spec.node_t -> t