package diffast-langs-verilog-parsing

You can search for identifiers within the package.

in-package search v0.2.0

diffast-langs-verilog-parsing
- Verilog_parsing
  - Ast
    
    c
    
    node
  - Common
  - Context
    
    stack
  - Label
  - Label_common
  - Labels
    
    AlwaysSpec
    
    AssignmentOperator
    
    BinaryOperator
    
    BinsSpec
    
    CompilerDirective
    
    ConcurrentAssertion
    
    DataType
    
    DeferredImmediateAssertion
    
    EventExpression
    
    Expression
    
    Gate
    
    IncOrDecOperator
    
    JoinSpec
    
    ModuleSpec
    
    NetType
    
    OverloadOperator
    
    PortDirection
    
    PropertyExpression
    
    Qualifier
    
    SequenceExpression
    
    SimpleImmediateAssertion
    
    Statement
    
    Strength
    
    SystemTask
    
    TimingCheck
    
    UnaryOperator
  - Lib
    
    parser_c
  - Macro
    
    table
  - Parser
    
    Make
    
    Incremental
    
    MenhirInterpreter
    
    Stat
  - Parser_aux
    
    F
    
    Stat
    
    STATE_T
    
    env
  - Printer
  - Scanner
    
    F
    
    A
    
    Stat
    
    TBF
    
    A
    
    Tok
    
    U
    
    Aux
    
    T
    
    branching_buffer
    
    buffer
    
    buffer_base
    
    c
    
    tokensource
    
    U
    
    Aux
    
    T
    
    c
  - Source
    
    c
  - Token
    
    F
    
    Stat
  - Tokenbuffer
    
    F
    
    A
    
    Stat
    
    Tok
    
    U
    
    Aux
    
    T
    
    branching_buffer
    
    buffer
    
    buffer_base
    
    c
    
    tokensource
  - Tokens
    
    Make
    
    MenhirInterpreter
    
    Stat
  - Tokens_
    
    T
    
    MenhirInterpreter
  - Ulexer
    
    F
    
    Aux
    
    Stat
    
    T

Legend:
Library
Module
Module type
Parameter
Class
Class type

module Fname = Langs_common.Fname

module Env_base = Langs_common.Env_base

module L = Label

type vartype =

| VTdefault
| VTtype

type memtbl = (Common.identifier, identifier_attribute) Hashtbl.t

and identifier_attribute =

| IAclass of memtbl ref
| IAcovergroup
| IApackage
| IAtype
| IAproperty
| IAclocking
| IAextern_method
| IAinterface

val iattr_to_str : identifier_attribute -> string

exception Attrs_found of identifier_attribute list

type scope_attribute =

| SApackage of Common.identifier
| SAclass of Common.identifier
| SAfunction of Common.identifier
| SAother

val sattr_to_str : scope_attribute -> string

type frame = {

f_attr : scope_attribute;
f_tbl : (Common.identifier, identifier_attribute) Hashtbl.t;

}

val create_frame : scope_attribute -> frame

val copy_frame : frame -> frame

val dummy_tbl : (Common.identifier, identifier_attribute) Hashtbl.t

val builtin_packages : (string * (string * identifier_attribute) list) list

val base_symbol_tbl : (Common.identifier, frame) Hashtbl.t

exception Frame_found of frame

type state = {

s_symbol_tbl : (Common.identifier, frame) Hashtbl.t;
s_stack : frame Stack.t;
s_scoped_flag : bool;
s_pvstate : int;
s_vartype : vartype;
s_in_table : bool;

}

val mkstate : 
  (Common.identifier, frame) Hashtbl.t ->
  frame Stack.t ->
  bool ->
  int ->
  vartype ->
  bool ->
  state

val top_key : Verilog_parsing.Ast.Loc.t

class env : object ... end

module type STATE_T = sig ... end

module F (Stat : STATE_T) : sig ... end