diffast-langs-verilog-parsing 0.1.1

inherit PB.c

val mutable context_stack : C.stack

val mutable begin_scope : unit -> unit

val mutable end_scope : unit -> unit

val mutable parser_partial_description_list : (Verilog_parsing.Tokens_.token
                                               * Lexing.position
                                               * Lexing.position,
                                                Verilog_parsing.Ast.partial)
                                                MenhirLib.Convert.revised

val mutable parser_partial_module_item_list : (Verilog_parsing.Tokens_.token
                                               * Lexing.position
                                               * Lexing.position,
                                                Verilog_parsing.Ast.partial)
                                                MenhirLib.Convert.revised

val mutable parser_partial_generate_item_list : (Verilog_parsing.Tokens_.token
                                                 * Lexing.position
                                                 * Lexing.position,
                                                  Verilog_parsing.Ast.partial)
                                                  MenhirLib.Convert.revised

val mutable parser_partial_block_decl_stmt_list : (Verilog_parsing.Tokens_.token
                                                   * Lexing.position
                                                   * Lexing.position,
                                                    Verilog_parsing.Ast.partial)
                                                    MenhirLib.Convert.revised

val mutable parser_partial_case_item_list : (Verilog_parsing.Tokens_.token
                                             * Lexing.position
                                             * Lexing.position,
                                              Verilog_parsing.Ast.partial)
                                              MenhirLib.Convert.revised

val mutable parser_partial_case_inside_item_list : (Verilog_parsing.Tokens_.token
                                                    * Lexing.position
                                                    * Lexing.position,
                                                     Verilog_parsing.Ast.partial)
                                                     MenhirLib.Convert.revised

val mutable parser_partial_cellpin_list : (Verilog_parsing.Tokens_.token
                                           * Lexing.position
                                           * Lexing.position,
                                            Verilog_parsing.Ast.partial)
                                            MenhirLib.Convert.revised

val mutable parser_partial_list_of_ports : (Verilog_parsing.Tokens_.token
                                            * Lexing.position
                                            * Lexing.position,
                                             Verilog_parsing.Ast.partial)
                                             MenhirLib.Convert.revised

val mutable parser_partial_pev_expr : (Verilog_parsing.Tokens_.token
                                       * Lexing.position
                                       * Lexing.position,
                                        Verilog_parsing.Ast.partial)
                                        MenhirLib.Convert.revised

val mutable parser_partial_ev_expr : (Verilog_parsing.Tokens_.token
                                      * Lexing.position
                                      * Lexing.position,
                                       Verilog_parsing.Ast.partial)
                                       MenhirLib.Convert.revised

val mutable parser_partial_expr : (Verilog_parsing.Tokens_.token
                                   * Lexing.position
                                   * Lexing.position,
                                    Verilog_parsing.Ast.partial)
                                    MenhirLib.Convert.revised

val mutable parser_main : (Verilog_parsing.Tokens_.token
                             Langs_common.Parserlib_base.token,
                            Verilog_parsing.Ast.node)
                            MenhirLib.Convert.revised

val mutable parse_error : Lexing.position ->
  Lexing.position ->
  ('a, unit, string, Verilog_parsing.Ast.node) format4 ->
  'a

val mutable scanner : < enter_source : 
                        Verilog_parsing.Source.c ->
                        Sedlexing.lexbuf
  ; get_token : 
    unit ->
    Verilog_parsing.Tokens_.token Langs_common.Parserlib_base.token >

val mutable _parse : unit -> Verilog_parsing.Ast.c

method set_ignore_include_flag : unit

method clear_ignore_include_flag : unit

method dump_ignored_regions : unit

method ignored_LOC : int

method dump_missed_regions : unit

method missed_LOC : int

method partial_parser_selector : C.t ->
  (Verilog_parsing.Tokens_.token * Lexing.position * Lexing.position,
    Verilog_parsing.Ast.partial)
    MenhirLib.Convert.revised

method parser_init : unit

method _parse : Verilog_parsing.Ast.c

method macrotbl : Verilog_parsing.Macro.table

method set_predefined_macrotbl : Verilog_parsing.Macro.table option -> unit

method make_source : PB.Storage.file -> Verilog_parsing.Source.c

method make_source_stdin : Verilog_parsing.Source.c

method __parse : Verilog_parsing.Ast.c

package diffast-langs-verilog-parsing