package hardcaml_step_testbench

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package hardcaml_step_testbench
Legend:
Library
Module
Module type
Parameter
Class
Class type

Parameters

Signature

module Input : sig ... end
module Output : sig ... end
module Logic : sig ... end
module Ops : sig ... end
val create_clock : ?initial_delay:int -> time:int -> Logic.t Event_driven_sim.Simulator.Signal.t -> Event_driven_sim.Simulator.Process.t
val create : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> t
type testbench = {
  1. ports_and_processes : t;
  2. simulator : Event_driven_sim.Simulator.t;
}
val with_processes : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
val with_vcd : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> vcd:Core.Out_channel.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
val with_waveterm : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> Hardcaml_event_driven_sim.Waveterm.Waveform.t * testbench
val expect : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> ?vcd:string -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
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