package hardcaml_step_testbench

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package hardcaml_step_testbench
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Module Simulator.With_interfaceSource

Parameters

Signature

Sourcemodule Input : sig ... end
Sourcemodule Output : sig ... end
Sourcemodule Logic : sig ... end
Sourcemodule Ops : sig ... end
Sourcetype t = {
  1. processes : Event_driven_sim.Simulator.Process.t list;
  2. input : Logic.t Hardcaml_event_driven_sim.Port.t Input.t;
  3. output : Logic.t Hardcaml_event_driven_sim.Port.t Output.t;
  4. internal : Logic.t Hardcaml_event_driven_sim.Port.t list;
}
Sourceval create_clock : ?initial_delay:int -> time:int -> Logic.t Event_driven_sim.Simulator.Signal.t -> Event_driven_sim.Simulator.Process.t
Sourceval create : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> t
Sourcetype testbench_processes = Logic.t Hardcaml_event_driven_sim.Port.t Input.t -> Logic.t Hardcaml_event_driven_sim.Port.t Output.t -> Event_driven_sim.Simulator.Process.t list
Sourcetype testbench = {
  1. ports_and_processes : t;
  2. simulator : Event_driven_sim.Simulator.t;
}
Sourceval with_processes : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
Sourceval with_vcd : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> vcd:Core.Out_channel.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
Sourceval with_waveterm : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> Hardcaml_event_driven_sim.Waveterm.Waveform.t * testbench
Sourceval expect : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> ?vcd:string -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench