package hardcaml_event_driven_sim

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hardcaml_event_driven_sim
- Hardcaml_event_driven_sim
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hardcaml_event_driven_sim.kernel
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Module
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Class type

Event_driven_simulator is an interface for writing event driven simulators (the main user is hardcaml-event-driven-sim). The simulator frameworks' semantics largely resembles those of VHDL.

module type Value_S = sig ... end

module Signal_id : sig ... end

module Signal : sig ... end

module Process : sig ... end

type t

val create : Process.t list -> t

Creates a new simulator running given processes.

val current_time : t -> int

val step : t -> unit

Advances time to the next time step.

val delta_step : t -> unit

Advances time a single delta step.

val stabilise : t -> unit

Advances time until there are no updates scheduled.

val next_scheduled_time : t -> int option

At what time next event in the queue is scheduled?

val (!!) : 't Signal.t -> 't

Read current value of a signal (same as Signal.read)

val (!&) : 't Signal.t -> Signal_id.t

Returns id of a signal.

Schedule a change to a signal without any delay.

val set : 't Signal.t -> 't -> unit

val (<--) : 't Signal.t -> 't -> unit

val set_after : 't Signal.t -> 't -> delay:int -> unit

Schedule a change to a signal after a delay.

The behaviour of this delay is the same as of VHDL transport delay.

val (<---) : 't Signal.t -> 't -> delay:int -> unit

val run : t -> time_limit:int -> unit

Run a simulation until time time_limit.

module Expert : sig ... end

module Async : sig ... end

Async-like wrapper around schedule_call and schedule_on_change.

module Change_monitor : sig ... end

module Debug : sig ... end

module Version_signal : sig ... end

A signal that keeps track of the state of some external data.