package hardcaml_axi

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package hardcaml_axi
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module X : sig ... end

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A simplified protocol for reading from and writing to slave space within a hardware design. Reads and writes are framed by _valid and _first signals. The _valid signal will be high throughout the transaction, while _first will toggle high only on the first cycle of a transaction. The _ready signals, driven by the slave, indicate completion of a transaction.

module Slave_statemachine : sig ... end

Statemachine for conversion between AXI transfers, and the simplified protocol defined by Internal_bus

module Master_statemachine : sig ... end

Statemachine for conversion from Ibus to AXI lite, with the Ibus as the master.

module Demultiplexer : sig ... end

Convert a single AXI address range into multiple interface slave spaces.

module Ram_with_byte_enables : sig ... end

RAM with per byte enable and configurable size

module Register_bank : sig ... end

Register bank attached directly to the AXI bus. Under the hood, this uses Internal_bus.Register_bank

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