package hardcaml_axi

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package hardcaml_axi
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RAM with per byte enable and configurable size

val sexp_of_t : t -> Sexplib0.Sexp.t
val create : Hardcaml.Scope.t -> reg_spec:Hardcaml.Reg_spec.t -> axi_master:Hardcaml.Signal.t Master_to_slave.t -> size:Base.int -> t
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