package hardcaml_axi

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package hardcaml_axi
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Module Internal_bus.W32Source

With 32 bit data and address bus

Sourcemodule Master_to_slave : sig ... end

A simpler master to slave interface decoded from AXI requests.

Sourcemodule Slave_to_master : sig ... end

A simpler slave to master interface to be encoded to AXI response.

Sourcemodule Demultiplexer : sig ... end

Demultiplex one master across one or more slaves.

Sourcemodule Ram_with_byte_enables : sig ... end

RAM with per byte enable and configurable size.

Sourcemodule Register_bank : sig ... end

Bank of read/write registers connected to a Master interface.

Sourcemodule Register : sig ... end

A simple state machine to register the datapath of an Ibus.