package hardcaml_axi

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With 32 bit data and address bus

module Master_to_slave : sig ... end

A simpler master to slave interface decoded from AXI requests.

module Slave_to_master : sig ... end

A simpler slave to master interface to be encoded to AXI response.

module Demultiplexer : sig ... end

Demultiplex one master across one or more slaves.

module Ram_with_byte_enables : sig ... end

RAM with per byte enable and configurable size.

module Register_bank : sig ... end

Bank of read/write registers connected to a Master interface.

module Register : sig ... end

A simple state machine to register the datapath of an Ibus.

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