package hardcaml_axi

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package hardcaml_axi
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A simplified protocol for reading from and writing to slave space within a hardware design. Reads and writes are framed by _valid and _first signals. The _valid signal will be high throughout the transaction, while _first will toggle high only on the first cycle of a transaction. The _ready signals, driven by the slave, indicate completion of a transaction.

module Master_to_slave : sig ... end

A simpler master to slave interface decoded from AXI requests.

module Slave_to_master : sig ... end

A simpler slave to master interface to be encoded to AXI response.

module Demultiplexer : sig ... end

Demultiplex one master across one or more slaves.

module Ram_with_byte_enables : sig ... end

RAM with per byte enable and configurable size.

module Register_bank : sig ... end

Bank of read/write registers connected to a Master interface.

module Register : sig ... end

A simple state machine to register the datapath of an Ibus.

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