module Always : sig ... endAlways is a DSL that lets one describe a circuit in the same style as a Verliog always block.
module Architecture : sig ... endHardware architecture specification.
module Bits : sig ... endAn immutable finite sequence of bits with a specified width.
module Build_mode : sig ... endSpecify whether to configure the hardware for simulation or synthesis.
module Caller_id : sig ... endEmbed the callstack in the signal type when it is created.
module Circuit : sig ... endCreation and manipulation of hardware circuits
module Circuit_database : sig ... endA database which holds a collection of circuits, indexed by a unique circuit name.
module Circuit_utilization : sig ... endUtilization information for a circuit which can be printed to a sexp.
module Comb : sig ... endCombinational logic API.
module Combinational_op : sig ... endA custom combinational operation that can be inserted into a simulation.
module Combinational_ops_database : sig ... endA database which holds a collecton of custom combinational operations for use with Cyclesim based simulators.
module Constant : sig ... endRepresentation of variable width Constants and conversion to/from OCaml types.
module Cosim : sig ... endIcarus Verilog Cosimulation interface (DEPRECATED)
module Cosim2 : sig ... endIcarus Verilog Cosimulation interface (DEPRECATED)
module Cyclesim : sig ... endCycle accurate simulator
module Cyclesim_float_ops : sig ... endFloating point operations for simulation.
module Design_rule_checks : sig ... endSimple circuit analsysis passes for common issues.
module Dedup : sig ... endDeduplicates combinatorial nodes performing redundant computation.
module Edge : sig ... endSpecification of rising or falling edge of a signal (normally a clock).
module Fifo : sig ... endSynchronous FIFO implementions with optional showahead functionality and pipelining stages.
module Fixed : sig ... endBits type with an explicit notion of a fixed point.
module Graph : sig ... endWrite circuit as graph.
module Hierarchy : sig ... endAllow a hardcaml circuit to be defined as a hierarchy of modules, rather than just a single flat module.
module IntbitsList : sig ... endBits described as lists of ints ie 0;1;1;1;0 - width implicit as length of list
module Interface : sig ... endInterfaces specify the widths and names of a group of signals, and some functions for manipulating the signals as a group.
module Instantiation : sig ... endInstantiation of sub-modules.
module Level : sig ... endSpecification of a signals level - high or low.
module Mangler : sig ... endMap a set of names to a set of unique names.
module Parameter : sig ... endA Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.
module Parameter_name : sig ... endRTL name of parameters on instantiated modules.
module Ram : sig ... endRandom access memories described using RTL inference.
module Recipe : sig ... endHardware generation in an imperative style.
module Reg_spec : sig ... endDefinition of clock, reset and clear signals for sequential logic (ie registers).
module Reserved_words : sig ... endTables of reserved words in Verilog, VHDL and OCaml.
module Rtl : sig ... endVHDL and Verilog netlist generation
module Rtl_attribute : sig ... endRTL attribute specification. Only relevant to downstream tooling.
module Scope : sig ... endScopes control the process of hierarchical circuit generation.
module Side : sig ... endUsed to specify when an operation should be performed - before or after an event like a clock edge.
module Signal : sig ... endHardware design datatype suitable for simulation and netlist generation
module Signal_graph : sig ... endA Signal_graph.t is a created from a list of signals, and defined by tracing back to inputs (unassigned wires or constants). Functions are provided for traversing the graph.
module Structural : sig ... endHardware generation API that includes tri-states - used for toplevel module generation.
module Transform : sig ... endTransform circuits to a different representation.
module Vcd : sig ... endVCD (Verilog Change Dump) generation
module With_valid : sig ... endUses a valid bit to indicate the validity of a value. Conceptually similar to an Option.t.
module Xilinx : sig ... endval sexp_of_array : ('a -> Base.Sexp.t) -> 'a Base.array -> Base.Sexp.tThese are exposed for code that does @@deriving sexp_of, hardcaml.
val sexp_of_list : ('a -> Base.Sexp.t) -> 'a Base.list -> Base.Sexp.t