package hardcaml

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package hardcaml
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Module Hardcaml.Ram

Random access memories described using RTL inference.

Can be specified with arbitrary numbers of read and write ports, though in reality only up to 1 of each can be inferred by a synthesizer.

module Collision_mode : sig ... end
module Write_port : sig ... end
module Read_port : sig ... end
val create : collision_mode:Collision_mode.t -> size:Base.Int.t -> write_ports:Write_port.t Base.Array.t -> read_ports:Read_port.t Base.Array.t -> Signal.t Base.Array.t
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