package hardcaml

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package hardcaml
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Write circuit as graph.

val write_dot_rank : Stdio.Out_channel.t -> Circuit.t -> Base.Unit.t
val write_gdl : ?names:Base.Bool.t -> ?widths:Base.Bool.t -> ?consts:Base.Bool.t -> ?clocks:Base.Bool.t -> Stdio.Out_channel.t -> Circuit.t -> Base.Unit.t

write a GDL (graph description language) file of the given circuit

val aisee3 : ?args:Base.String.t -> ?names:Base.Bool.t -> ?widths:Base.Bool.t -> ?consts:Base.Bool.t -> ?clocks:Base.Bool.t -> Circuit.t -> Base.Unit.t

launch aisee3 to visualize the given circuit

  • deprecated [since 2017-11] aisee3 is no longer available.
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