Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

Assertions within Hardcaml simulations.

Optionally embed the callstack in the signal type when it is created.

Combinational logic API.

Representation of variable width Constants and conversion to/from OCaml types.

Interfaces specify the widths and names of a group of signals, and some functions for manipulating the signals as a group.

Instantiation of sub-modules.

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

RTL name of parameters on instantiated modules.

Scopes control the process of hierarchical circuit generation.

Hardware design datatype suitable for simulation and netlist generation

Hardware generation API that includes tri-states - used for toplevel module generation.

Creation and manipulation of hardware circuits

A database which holds a collection of circuits, indexed by a unique circuit name.

Utilization information for a circuit which can be printed to a sexp.

Allow a hardcaml circuit to be defined as a hierarchy of modules, rather than just a single flat module.

Map a set of names to a set of unique names.

An immutable finite sequence of bits with a specified width.

Combinational logic described as lists of Bits ie 0;1;1;1;0.

A custom combinational operation that can be inserted into a simulation.

A database which holds a collecton of custom combinational operations for use with Cyclesim based simulators.

Cycle accurate simulator

Floating point operations for simulation.

VCD (Verilog Change Dump) generation utilities, and a Cyclesim wrapper function.

How to display the value of a signal. Generally used in waveforms.

RTL attribute specification. Only relevant to downstream tooling.

Tables of reserved words in Verilog, VHDL and OCaml.

Simple circuit analsysis passes for common issues.

Deduplicates combinatorial nodes performing redundant computation.

A Signal_graph.t is a created from a list of signals, and defined by tracing back to inputs (unassigned wires or constants). Functions are provided for traversing the graph.

Hardware architecture specification.

Specify whether to configure the hardware for simulation or synthesis.

Specification of rising or falling edge of a signal (normally a clock).

The Enum contains functors that can be used to create special interface modules to represent an enumeration type (ie: a variant with no arguments).

Specification of a signals level - high or low.

A memory read port.

Used to specify when an operation should be performed - before or after an event like a clock edge.

A memory write port.

Simple and fast distributed RAM based asynchronous FIFO. The depth of the FIFO is parameterizable, however, it should be less than or equal to 2 ^ LUT_SIZE to avoid glitches on the addressing logic.

Synchronous FIFO implementions with optional showahead functionality and pipelining stages.

Random access memories described using RTL inference.