package hardcaml

You can search for identifiers within the package.

in-package search v0.2.0

RTL Hardware Design in OCaml

Install

dune-project

Dependency

github.com Readme Changelog MIT License Edit opam file Versions (9)

Authors

J

Jane Street Group, LLC

Maintainers

J

Jane Street developers

Sources

v0.17.1.tar.gz

md5=7435ee8610c2205c5f912b4bf09163b0

sha512=38d7cf428bd3491024212e52776ac582183d7b5f6a494589a3697d9a213fa18347d6eeea23327859c340b0cb3b967c08cd21a8a7f8d15cf2de20e5598cb8456d

doc/hardcaml/Hardcaml/Design_rule_checks/index.html

Module `Hardcaml.Design_rule_checks`Source

Simple circuit analsysis passes for common issues.

Source

val verify_clock_pins : 
  expected_clock_pins:Base.string Base.list ->
  Circuit.t ->
  Base.unit

Raises if there exists a seqential element (register or memory) whose clock input pin is not in expected_clock_pins. Clocks are defined by the name of input clock signals into the circuit.