package hardcaml

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RTL Hardware Design in OCaml

Install 

dune-project
 Dependency

github.com Readme Changelog MIT License Edit opam file Versions (9)

Authors

  1. J
    Jane Street Group, LLC

Maintainers

  1. J
    Jane Street developers

Sources

v0.17.1.tar.gz
md5=7435ee8610c2205c5f912b4bf09163b0
sha512=38d7cf428bd3491024212e52776ac582183d7b5f6a494589a3697d9a213fa18347d6eeea23327859c340b0cb3b967c08cd21a8a7f8d15cf2de20e5598cb8456d

doc/hardcaml/Hardcaml/Write_port/index.html

Module Hardcaml.Write_portSource

A memory write port.

Sourcetype 'a t = {
  1. write_clock : 'a;
  2. write_address : 'a;
  3. write_enable : 'a;
  4. write_data : 'a;
}
Sourceval sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t

A partial Interface implementation

Use with Interface.Update to create a full interface specification.

Sourceval iter : 'a t -> f:('a -> Base.unit) -> Base.unit
Sourceval iter2 : 'a t -> 'b t -> f:('a -> 'b -> Base.unit) -> Base.unit
Sourceval map : 'a t -> f:('a -> 'b) -> 'b t
Sourceval map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
Sourceval to_list : 'a t -> 'a Base.list
Sourceval port_names : Base.string t