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Source file pp_riscv.ml
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171openArch_declopenAsmTargetBuilderopenUtilsopenPrintCommonopenProgopenPrintASMopenAsm_utils(* Architecture imports*)openRiscv_declopenRiscv_instr_declletarch=riscv_declletimm_pre=""(* We support the following RISC-V memory accesses.
Offset addressing:
- A base register and an immediate offset (displacement):
#+/-<imm>(<reg>) (where + can be omitted).
*)letpp_reg_address_auxbasedispoffscal=match(disp,off,scal)with|None,None,None->Format.asprintf"(%s)"base|Somedisp,None,None->Format.asprintf"%s%s(%s)"imm_predispbase|_,_,_->hierror~loc:Lnone~kind:"assembly printing"~internal:true"the address computation is too complex: an intermediate variable might be needed"letpp_imm=pp_immimm_preletpp_register=pp_registerarchletpp_reg_addressaddr=letaddr=parse_reg_addressarchaddrinpp_reg_address_auxaddr.baseaddr.displacementaddr.offsetaddr.scaleletpp_condition_kind(ck:Riscv_decl.condition_kind)=matchckwith|EQ->"beq"|NE->"bne"|LTSigned->"blt"|LTUnsigned->"bltu"|GESigned->"bge"|GEUnsigned->"bgeu"letpp_cond_arg(ro:Riscv_decl.registeroption)=matchrowith|Somer->pp_registerr|None->"x0"letpp_asm_arg(arg:(register,Arch_utils.empty,Arch_utils.empty,Arch_utils.empty,condt)asm_arg)=matchargwith|Condt_->None|Imm(ws,w)->Some(pp_imm(Conv.z_of_wordwsw))|Regr->Some(pp_registerr)|Regx_->.|Addr(Aregra)->Some(pp_reg_addressra)|Addr(Aripr)->Some(pp_rip_addressr)|XReg_->.letpp_iname_ext_=""letpp_iname2_extext__=extletpp_ext=function|PP_error->assertfalse|PP_name->""|PP_inamews->pp_iname_extws|PP_iname2(s,ws1,ws2)->pp_iname2_extsws1ws2|PP_viname(ve,long)->assertfalse|PP_viname2(ve1,ve2)->assertfalse|PP_ctct->assertfalseletpp_name_extpp_op=Format.asprintf"%s%s"pp_op.pp_aop_name(pp_extpp_op.pp_aop_ext)moduleRiscVTarget:AsmTargetwithtypereg=Riscv_decl.registerandtyperegx=Arch_utils.emptyandtypexreg=Arch_utils.emptyandtyperflag=Arch_utils.emptyandtypecond=Riscv_decl.condtandtypeasm_op=Riscv_instr_decl.riscv_op=structtypereg=Riscv_decl.registertyperegx=Arch_utils.emptytypexreg=Arch_utils.emptytyperflag=Arch_utils.emptytypecond=Riscv_decl.condttypeasm_op=Riscv_instr_decl.riscv_op(* TODO_RISCV: Review. *)letheaders=[]letdata_segment_header=[Instr(".p2align",["5"]);Labelglobal_datas_label]letfunction_header=[Instr("addi",[pp_registerSP;pp_registerSP;"-4"]);Instr("sw",[pp_registerRA;pp_reg_address_aux(pp_registerSP)NoneNoneNone])]letfunction_tail=[Instr("lw",[pp_registerRA;pp_reg_address_aux(pp_registerSP)NoneNoneNone]);Instr("addi",[pp_registerSP;pp_registerSP;"4"]);Instr("ret",[])]letpp_instr_rfninstr=matchinstrwith|ALIGN->failwith"TODO_RISCV: pp_instr align"|LABEL(_,lbl)->[Label(string_of_labelfnlbl)]|STORELABEL(dst,lbl)->[Instr("adr",[pp_registerdst;string_of_labelfnlbl])]|JMPlbl->[Instr("j",[pp_remote_labellbl])]|JMPIarg->beginmatchargwith|RegRA->[Instr("ret",[])]|Regr->[Instr("jr",[pp_registerr])]|_->failwith"TODO_RISCV: pp_instr jmpi"end|Jcc(lbl,ct)->letiname=pp_condition_kindct.cond_kindinletcond_fst=pp_cond_argct.cond_fstinletcond_snd=pp_cond_argct.cond_sndin[Instr(iname,[cond_fst;cond_snd;string_of_labelfnlbl])]|JAL(RA,lbl)->[Instr("call",[pp_remote_labellbl])]|JAL_|CALL_|POPPC->assertfalse|SysCallop->[Instr("call",[Asm_utils.pp_syscallop])]|AsmOp(op,args)->letid=instr_descriscv_declriscv_op_decl(None,op)inletpp=id.id_pp_asmargsinletname=pp_name_extppinletargs=List.filter_map(fun(_,a)->pp_asm_arga)pp.pp_aop_argsin[Instr(name,args)]endmoduleRiscVPrinter=AsmTargetBuilder.Make(RiscVTarget)letprint_progfmtprog=PrintASM.pp_asmfmt(RiscVPrinter.asm_of_progprog)