package hardcaml_xilinx_reports

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package hardcaml_xilinx_reports
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Define properties of clocks on the top level module. The most important properties are the clock net name and it's period.

We also allow specification of the input BUFG driving the clock pin. This is optional, but allows the synthesizer to approximate skew across the device. It is specified at a bufg location constraint ie BUFGCTRL_X0Y2.

type t
val create : ?clk_src_bufg:Base.String.t -> name:Base.String.t -> period:Base.Float.t -> Base.Unit.t -> t

Create a clock with the period specified in nanoseconds.

val create_mhz : ?clk_src_bufg:Base.String.t -> name:Base.String.t -> frequency_mhz:Base.Float.t -> Base.Unit.t -> t

Create a clock with the frequency specified in MHz.

val name : t -> Base.String.t
val period : t -> Base.Float.t
val clk_src_bufg : t -> Base.String.t Base.Option.t
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