package hardcaml_step_testbench

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package hardcaml_step_testbench
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Module Hardcaml_step_testbenchSource

Hardcaml testbench infrastructure which allows multiple threads of execution to be interleaved and synchronised at each clock cycle while interacting with the ports of a simulation.

Inputs set to Bits.empty are assumed to be unset and may be set in parent tasks. If no task sets an input then the port will either keep its previous value, or be set to a known default value depending on the input_default argument to the run function.

Inputs set in a child task take precendence over inputs sets in parent tasks.

Sourcemodule type S = sig ... end
Sourcemodule Before_and_after_edge : sig ... end
Sourcemodule Make (I : Hardcaml.Interface.S) (O : Hardcaml.Interface.S) : S with module I := I and module O := O