package hardcaml_step_testbench

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module type S = sig ... end
type ('i, 'o) t_

t is mostly abstract, but we expose is as a constructor so that the type checker knows that t is injective.

type ('i, 'o) t =
  1. | T of ('i, 'o) t_
val sexp_of_t : ('i -> Sexplib0.Sexp.t) -> ('o -> Sexplib0.Sexp.t) -> ('i, 'o) t -> Sexplib0.Sexp.t
type ('i, 'o) t_module = (module S with type Input.t = 'i and type Output.t = 'o)
val sexp_of_input : ('i, _) t -> 'i -> Digital_components__.Import.Sexp.t
val sexp_of_output : (_, 'o) t -> 'o -> Digital_components__.Import.Sexp.t
val input_module : ('i, _) t -> 'i Data.t
val output_module : (_, 'o) t -> 'o Data.t
val create : ('i, 'o) t_module -> ('i, 'o) t
val output : ('i, 'o) t -> 'i -> 'o

output returns the output based on an input and its current state, but does not update the state. A component is called "combinational" if output t i ignores t. A component is called "sequential" if output t i uses t. A sequential component is called a "moore machine" if it ignores i and a "mealy machine" if it uses i.

val update_state : ('i, _) t -> 'i -> Digital_components__.Import.Unit.t

update_state updates t's state based on an input and its current state

val run_with_inputs : ('i, 'o) t -> 'i Digital_components__.Import.List.t -> ('i * 'o) Digital_components__.Import.List.t

run_with_inputs t is runs length is steps with t, on each step calling update_state and then output, pairing the input of that step with the output.

module Next_input : sig ... end
val run_until_finished : ?show_steps:Digital_components__.Import.Bool.t -> ('i, 'o) t -> first_input:'i -> next_input:('o -> 'i Next_input.t) -> Digital_components__.Import.Unit.t

Component combinators

val sequence : ('a, 'b) t -> ('b, 'c) t -> ('a, 'c) t
val map_input : ('i2, 'o) t -> 'i1 Data.t -> f:('i1 -> 'i2) -> ('i1, 'o) t
val map_output : ('i, 'o1) t -> 'o2 Data.t -> f:('o1 -> 'o2) -> ('i, 'o2) t

Combinational components

module Combinational : sig ... end
val create_combinational : ('i, 'o) Combinational.t -> ('i, 'o) t
val and_ : (Digital_components__.Import.Bool.t * Digital_components__.Import.Bool.t, Digital_components__.Import.Bool.t) t
val or_ : (Digital_components__.Import.Bool.t * Digital_components__.Import.Bool.t, Digital_components__.Import.Bool.t) t
val not_ : (Digital_components__.Import.Bool.t, Digital_components__.Import.Bool.t) t

Sequential components

val flip_flop : Digital_components__.Import.Unit.t -> (Digital_components__.Import.Bool.t, Digital_components__.Import.Bool.t) t
module Flip_flop_with_load_enable : sig ... end
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