package hardcaml_step_testbench

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package hardcaml_step_testbench
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Module Hardcaml_step_testbench.MakeSource

Parameters

Signature

Sourcemodule Simulator : sig ... end

A simulator for the design being tested.

Sourcemodule O_data : sig ... end

A testbench takes the circuit's output as its input and produces its output as input for the circuit. An 'a t describes a testbench computation that takes zero or more steps and produces a value of type 'a.

val (>>=) : 'a t -> ('a -> 'b t) -> 'b t
val (>>|) : 'a t -> ('a -> 'b) -> 'b t
module Monad_infix : sig ... end
val bind : 'a t -> f:('a -> 'b t) -> 'b t
val return : 'a -> 'a t
val map : 'a t -> f:('a -> 'b) -> 'b t
val join : 'a t t -> 'a t
val ignore_m : 'a t -> unit t
val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t
module Let_syntax : sig ... end
Sourceval cycle : ?num_cycles:Hardcaml_step_testbench__.Import.Int.t -> I_data.t -> O_data.t t

cycle i_data ~num_cycles waits for num_cycles cycles of the simulator to run, applying i_data to the simulator input ports, and returns the output computed in the final cycle. cycle raises if num_cycles < 1.

Sourceval for_ : Hardcaml_step_testbench__.Import.Int.t -> Hardcaml_step_testbench__.Import.Int.t -> (Hardcaml_step_testbench__.Import.Int.t -> Hardcaml_step_testbench__.Import.Unit.t t) -> Hardcaml_step_testbench__.Import.Unit.t t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

Sourceval delay : I_data.t -> num_cycles:Hardcaml_step_testbench__.Import.Int.t -> Hardcaml_step_testbench__.Import.Unit.t t

delay inputs ~num_cycles applies inputs for num_cycles clock cycles and then returns unit. delay raises if num_cycles < 0.

Sourceval spawn : (O_data.t -> 'a t) -> ('a, I_data.t) finished_event t

Launch a new task within the current simulation step.

Sourceval merge_inputs : parent:I_data.t -> child:I_data.t -> I_data.t

merge_inputs ~parent ~child merges the child inputs into the parent. If a child input is empty, the parent's value is used.

Sourceval spawn_io : inputs:(parent:'i -> child:I_data.t -> 'i) -> outputs:('o -> Hardcaml.Bits.t O.t) -> (O_data.t -> 'a t) -> (('a, I_data.t) finished_event, 'o Before_and_after_edge.t, 'i) Digital_components.Step_monad.t

Launch a task from a testbench with a cycle funtion taking 'i to 'o. The inputs and outputs arguments should construct I_data.t and O_data.t from the types of the child testbench.

Sourceval wait_for : ('a, 'b) finished_event -> 'a t

Wait for the given event to occur, and extract its return value.

Sourceval wait_for_with_timeout : ('a, 'b) finished_event -> timeout_in_cycles:Hardcaml_step_testbench__.Import.Int.t -> 'a Hardcaml_step_testbench__.Import.Option.t t

Like wait_for except it stops waiting after timeout_in_cycles and returns None. Note that the spawned task continues to execute.

Sourceval input_hold : Hardcaml.Bits.t I.t

Call run ~input_default:input_hold to hold inputs their previous value if they are unset by tasks in the testbench.

Sourceval input_zero : Hardcaml.Bits.t I.t

Call run ~input_default:input_zero to set inputs to zero if unset by tasks in the testbench.

Sourceval run_with_timeout : ?input_default:Hardcaml.Bits.t I.t -> ?show_steps:Hardcaml_step_testbench__.Import.Bool.t -> ?timeout:Hardcaml_step_testbench__.Import.Int.t -> Hardcaml_step_testbench__.Import.Unit.t -> simulator:Simulator.t -> testbench:(O_data.t -> 'a t) -> 'a Hardcaml_step_testbench__.Import.Option.t

Run the testbench until the main task finishes. The input_default argument controls what should happen if an input is unset by tasks in the testbench on any particular cycle. If a field is set to Bits.empty then the previous value should be held. Otherwise, the value provided is used as the default value for that field.

The optional timeout argument stops the simulation after the given number of steps and returns None. Otherwise it will continue until the testbech completes.

Sourceval run_until_finished : ?input_default:Hardcaml.Bits.t I.t -> ?show_steps:Hardcaml_step_testbench__.Import.Bool.t -> Hardcaml_step_testbench__.Import.Unit.t -> simulator:Simulator.t -> testbench:(O_data.t -> 'a t) -> 'a

Run the testbench until completion.

Sourcemodule List : sig ... end
Sourcemodule Array : sig ... end