package hardcaml

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RTL Hardware Design in OCaml

Install

dune-project
 Dependency

Authors

Maintainers

Sources

v0.17.1.tar.gz
md5=7435ee8610c2205c5f912b4bf09163b0
sha512=38d7cf428bd3491024212e52776ac582183d7b5f6a494589a3697d9a213fa18347d6eeea23327859c340b0cb3b967c08cd21a8a7f8d15cf2de20e5598cb8456d

Description

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

Added to opam-repository:

README

"Hardcaml"

Hardcaml is an OCaml library for designing and testing hardware designs.

  • Express hardware designs in OCaml
  • Make generic designs using higher order functions, lists, maps, functors...
  • Simulate designs in OCaml
  • Convert to (hierarchical) Verilog or VHDL
  • Write new modules to transform or analyse circuits, or provide new backends

Install

$ opam install hardcaml ppx_hardcaml hardcaml_waveterm

Documentation

Tools and libraries

  • Hardcaml_waveterm - ASCII based digital waveforms. Usable in expect tests or from an interactive terminal application.
  • Hardcaml_c - convert Hardcaml designs to C-based simulation models. Provides an API compatible with the standard Cyclesim module. Trades compilation time for runtime performance.
  • Hardcaml_verilator - Convert Hardcaml designs to very high speed simulation model using the open source Verilator compiler.
  • Hardcaml_step_testbench - Monadic testbench API. Control multiple tasks synchronized to a clock without converting to a statemachine coding style.
  • Hardcaml_circuits - A library of useful/interesting Hardcaml designs
  • Hardcaml_fixed_point - Fixed point arithmetic with rounding and overflow control
  • Hardcaml_xilinx - Various Xilinx primitives wrapped with Hardcaml interfaces and simulation models
  • Hardcaml_xilinx_components - Tool to read Xilinx unisim and xpm component definitions and generate Hardcaml interfaces
  • Hardcaml_of_verilog - Convert a verilog design to Hardcaml using Yosys
  • Hardcaml_verify - SAT based formal verification tools for Hardcaml
  • Hardcaml_xilinx_reports - Automated generation of synthesis reports from Vivado.

Projects using Hardcaml

Dependencies (10)

  1. zarith >= "1.11"
  2. ppxlib >= "0.36.0"
  3. dune >= "3.11.0"
  4. stdio >= "v0.17" & < "v0.18~"
  5. ppx_sexp_conv >= "v0.17" & < "v0.18~"
  6. ppx_jane >= "v0.17" & < "v0.18~"
  7. core_kernel >= "v0.17" & < "v0.18~"
  8. bin_prot >= "v0.17" & < "v0.18~"
  9. base >= "v0.17" & < "v0.18~"
  10. ocaml >= "5.3.0"

Dev Dependencies

None

Optional Dependencies

None

Conflicts

None

Build status

Results of building hardcaml with each compiler on check.ci.ocaml.org, run of against opam-repository 8a77e58. All results for this package.

Each result links to its build log. To keep crawlers from overloading the site, build logs require a GitHub sign-in (see ocurrent/opam-health-check). On your first log, GitHub asks you to “Authorize opam-health-check”, the OCurrent app that runs these checks; it sees only your public profile, not your repositories. The sign-in lasts 30 days.

Version OCaml 4.11 OCaml 4.14 OCaml 5.2 OCaml 5.4 OCaml 5.5
v0.17.1 (this version) n/a n/a n/a good good
v0.17.0 n/a n/a good n/a n/a
v0.16.0 n/a good good n/a n/a
v0.15.0 good good good n/a n/a
  • good Package successfully built
  • partial One of the dependencies failed to build
  • bad Package failed to build
  • n/a Package is not available in this environment
  • internal Internal failure