hardcaml v0.13.0 · OCaml Package

module Always : sig ... end

Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

module Architecture : sig ... end

module Bits : sig ... end

module Build_mode : sig ... end

module Caller_id : sig ... end

module Circuit : sig ... end

Creation and manipulation of hardware circuits

module Circuit_database : sig ... end

A database which holds a collection of circuits, indexed by a unique circuit name. The database is used to map occurrences of instantiations within a Hardcaml circuit to an implementation. This can then be used to generate an RTL module hierarchy. Structurally identical circuits may be indentified and the implementation shared.

module Circuit_utilization : sig ... end

module Comb : sig ... end

module Combinational_op : sig ... end

A custom combinational operation that can be inserted into a simulation.

module Combinational_ops_database : sig ... end

A database which holds a collecton of custom combinational operations for use with Cyclesim based simulators.

module Constant : sig ... end

module Cosim : sig ... end

Icarus Verilog Cosimulation interface

module Cosim2 : sig ... end

module Cyclesim : sig ... end

module Cyclesim_float_ops : sig ... end

module Design_rule_checks : sig ... end

module Dedup : sig ... end

module Edge : sig ... end

module Fifo : sig ... end

Synchronous FIFO.

module Fixed : sig ... end

module Graph : sig ... end

Write circuit as graph. Currently works quite well with aisee3; www.aisee.com

module Hierarchy : sig ... end

module IntbitsList : sig ... end

bits described as lists of ints ie 0;1;1;1;0 - width implicit as length of list

module Interface : sig ... end

module Instantiation : sig ... end

module Level : sig ... end

module Mangler : sig ... end

Map a set of names to a set of unique names.

module Parameter : sig ... end

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

module Parameter_name : sig ... end

module Ram : sig ... end

module Recipe : sig ... end

module Reg_spec : sig ... end

module Reserved_words : sig ... end

module Rtl : sig ... end

module Rtl_attribute : sig ... end

RTL attribute specification. Only relevant to downstream tooling.

module Scope : sig ... end

module Side : sig ... end

module Signal : sig ... end

module Signal_graph : sig ... end

A Signal_graph.t is a created from a list of signals, and defined by tracing back to inputs (unassigned wires or constants). Functions are provided for traversing the graph.

module Structural : sig ... end

module Transform : sig ... end

module Vcd : sig ... end

VCD (Verilog Change Dump) generation

module With_valid : sig ... end

Uses a valid bit to indicate the validity of a value. Conceptually similar to an Option.t.

module Xilinx : sig ... end

val sexp_of_array : ('a -> Base.Sexp.t) -> 'a Base.array -> Base.Sexp.t

These are exposed for code that does @@deriving sexp_of, hardcaml.

val sexp_of_list : ('a -> Base.Sexp.t) -> 'a Base.list -> Base.Sexp.t

package hardcaml