package hardcaml

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package hardcaml
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type task = Base.Unit.t -> Base.Unit.t
val create : in_ports:Port_list.t -> out_ports_before_clock_edge:Port_list.t -> out_ports_after_clock_edge:Port_list.t -> internal_ports:Port_list.t -> reset:task -> cycle_check:task -> cycle_comb0:task -> cycle_seq:task -> cycle_comb1:task -> lookup_signal:(Signal.Uid.t -> Bits.t Base.Ref.t) -> lookup_reg:(Signal.Uid.t -> Bits.t Base.Ref.t) -> t_port_list
module Step : sig ... end
val modify : ('i, 'o) t -> (Side.t * Step.t * task) Base.List.t -> ('i, 'o) t
val coerce : (Port_list.t, Port_list.t) t -> to_input:(Port_list.t -> 'i) -> to_output:(Port_list.t -> 'o) -> ('i, 'o) t
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