fsml

A library for describing and describing synchronous finite state machines
IN THIS PACKAGE
Module Fsml . Tevents

Timed event sets

type t = Event.t list Clock.clocked

A timed event set (TES) is a list of events occuring at a given clock cycle. Example 4, [x:=1,y:=1] means that both x and y take value 1 at clock cycle 4. TES are used by simulator both to represent input stimuli and output events

module Ops : sig ... end
val merge : t list list -> t list

merge [st1; ...: stn] merges n sequences of TES wrt. clock cycles. In other words, merge [l1; l2; ...; ln] is l1 @@@ l2 @@@ ... @@@ ln.

Wrappers

val changes : string -> Expr.e_val Clock.clocked list -> t list

changes name vcs builds a list of TES from a list vcs of value changes related to signal name, a value change being a pair of the clk cycle and a value. Ex: changes "x" [0,Int 1; 2,Int 0] is [0,[x:=1]; 2,[x:=0]].

Printing

val to_string : t -> string