hardcaml 1.2.0 · OCaml Package

type name = string

type id = int

type width = int

type signal =

| Empty
| Module_input of id * name * width
| Module_output of id * name * width * signal Stdlib.ref
| Module_tristate of id * name * width * signal list Stdlib.ref
| Internal_wire of id * width * signal Stdlib.ref
| Internal_triwire of id * width * signal list Stdlib.ref
| Instantiation_output of id * name
| Instantiation_tristate of id * name
| Instantiation of id * name * (string * generic) list * (string * signal) list * (string * signal) list * (string * signal) list
| Rtl_op of id * width * rtl_op

and rtl_op =

| Constant of string
| Select of int * int * signal
| Concat of signal list
| Mux of signal * signal list

and generic =

| GInt of int
| GFloat of float
| GString of string
| GUnquoted of string

type circuit = {

name : string;
id : id;
mutable signals : signal list;

}

exception Invalid_submodule_input_connection of string * string * signal

exception Invalid_submodule_output_connection of string * string * signal

exception Invalid_submodule_tristate_connection of string * string * signal

exception Wire_already_assigned of signal

exception Invalid_assignment_target of signal

exception Cant_assign_wire_with of signal

exception Cant_assign_triwire_with of signal

exception Invalid_name of signal

exception Invalid_width of signal

exception Invalid_id of signal

exception Invalid_constant of string

exception Rtl_op_arg_not_readable of signal

exception Too_few_mux_data_elements

exception Too_many_mux_data_elements of int

exception All_mux_data_elements_must_be_same_width of int list

exception No_elements_to_concat

exception Select_index_error of int * int

exception Binop_arg_widths_different of string

exception No_circuit

exception Circuit_already_started

val circuit : string -> unit

val end_circuit : unit -> unit

val find_circuit : string -> circuit

val width : signal -> int

val mk_input : string -> int -> signal

val mk_output : string -> int -> signal

val mk_tristate : string -> int -> signal

val mk_wire : int -> signal

val mk_triwire : int -> signal

val (<==) : signal -> signal -> unit

val is_connected : signal -> bool

val inst : 
  ?g:(string * generic) list ->
  ?i:(string * signal) list ->
  ?o:(string * signal) list ->
  ?t:(string * signal) list ->
  string ->
  unit

val (==>) : 'a -> 'b -> 'a * 'b

val const : string -> signal

val constz : int -> signal

val mux : signal -> signal list -> signal

val concat : signal list -> signal

val select : signal -> int -> int -> signal

module type Config = sig ... end

val prefix : string

module Base (C : Config) : sig ... end

module Base0 : sig ... end

module Base1 : sig ... end

module Base2 : sig ... end

val write_verilog : (string -> unit) -> circuit -> unit

module Lib : sig ... end

package hardcaml